Mentor uses ADMS mixed-signal verification platform

Mentor Graphics corporation, announced two customer achievements using its ADVance MS (ADMS) mixed-signal verification platform. ADMS is a scalable platform that has been architected for mixed-signal functional verification. The platform integrates a suite of simulation tools, Eldo, Eldo RF, and ADiT for transistor-level simulation, as well as Questa for logic-level simulation. ADMS provides capabilities that enable designers to verify that their designs are correct in either a digital-centric or analog-centric design flow.

UMC, a semiconductor foundry, verified a complete transceiver reference design that included a combination of design representations such as digital languages, analog mixed-signal behavior languages, SPICE models and fast SPICE models (ADiT) by leveraging the seamless integration of various simulation engines offered via the ADMS platform.

Patrick Lin—chief SoC architect, system and architecture support—UMC, said, "Through our collaboration with Mentor, we validated a full chip mixed-signal transceiver reference design in our 130nm mixed-signal process using Mentor's ADMS technology. With the combination of our reference design and the ADMS methodology, we are providing our mixed-signal customers another approach to achieve our advanced mixed-signal processes. The combined methodology is slated to be demonstrated in a series of events starting with a demo at DAC 2007."

Jue-Hsien Chern, vice president and general manager for deep submicron division, Mentor Graphics, stated, "We are delighted that our customers achieved design success with our verification technologies. Through close collaboration with our partners, we have developed leading edge technologies for AMS SoC design."

Mentor Graphics