CebaTech announces first family of IP Cores based on CebaIP Platform

CebaTech has announced the availability of the GZIP family of CebaIP Cores(tm). The GZIP family provides comprehensive, standards-based, lossless data compression for use in storage and data networking ASICs and FPGAs. Integrating the GZIP family of IP cores onto storage and data networking integrated circuits (ICs) can greatly reduce the operational costs of storing and transmitting data by end users of these ICs. Designers can choose from a number of available configurations to meet their desired speed, compression efficiency, and area requirements.

Using the CebaIP Platform's integrated advanced direct memory access (DMA) controller with the OpenBSD software driver, designers are able to rapidly achieve complete compression, decompression, and encryption offload solutions.
The GZIP family is standards-based and conforms to the popular "deflate" standard as specified in RFC1951. File formats for both ZLIB and GZIP, as specified in RFC1950 and 1952, are also supported. Data rates range from 2Gb/s and scale to 8Gb/s while typical compression ratios for benchmark files sets are in the range of 2.5:1 to 3.5:1.

The GZIP family also includes optional advanced encryption standard (AES) capability with select cipher modes for securing "data at rest" inside the enterprise. AES data rates range from 3Gb/s and scale to 12Gb/s. Supported cipher modes include ECB, CBC, GCM, and XTS with keys sizes of 128b, 192b, and 512b. (XTS is the latest recommendation by the IEEE in the P1619 standard for encryption of storage devices.)

CebaTech