Synplicity announces breakthrough ASIC verification solution

Identify Pro software improves the productivity of existing verification methodologies, such as assertion-based verification and simulation resulting in a significantly reduced overall verification time with improved verification coverage and quality.

Working with popular simulation tools, such as Synopsys’ VCS, the Identify Pro solution automatically connects the prototype hardware with an existing software simulation environment in a transparent and seamless manner for comprehensive RTL code analysis and debug. The Identify Pro software provides initialization of the simulator and automatically creates a test bench from the actual stimulus of the FPGA-based prototype giving designers a verification solution that is orders of magnitude faster in performance than any other ASIC verification methodology.

The Identify Pro software allows ASIC and ASSP designers, using an FPGA-based prototype system, to functionally debug their design at hardware speed, directly in their RTL source code. This allows functional verification for RTL designs that is up to 10,000 times faster than RTL simulators and enables the use of “real-world” stimulus making it an ideal verification platform for applications like networking, audio, video, and all designs with large amounts of software content. Used in conjunction with Synplicity’s Synplify Premier physical synthesis tool, the Identify Pro software enables assertion synthesis into hardware and assertion debug.

The Identify Pro software offers the fastest method of finding errors in an FPGA or ASIC prototype by using live stimulus to quickly reach a trigger condition such as a functional bug or assertion failure. By using advanced triggering capabilities, including assertions, that are inserted into the RTL source code, design problems are found that could take a simulator days or weeks to uncover. Once a functional bug or assertion failure is found, the Identify Pro tool’s TotalRecall technology is used to initialize a standard software simulator with all signal and state values at a user-defined number of clock cycles prior to the trigger being reached. The complete module state, along with a test bench, is automatically exported to an RTL simulator where the user can replay the sequence and diagnose bugs in the original RTL source code. The Identify Pro product is ideal for ASIC verification teams using FPGA hardware as it allows them to quickly find functional errors in their design. With the coverage of real-world data and the speed of real hardware, the Identify Pro tool provides a comprehensive verification environment for finding, fixing, and verifying functional errors in FPGA and ASIC designs.

Synplicity, Inc.