Customizable processor replaces signal processing in embedded devices

Media signal processors for the latest digital TVs, mobile phones and DVD players often process streaming data for both image and voice. A signal processor for these embedded devices is typically configured as a combination of a dedicated circuit core and the processor core. For example, an MPEG-4 decoder is configured with a dedicated circuit core, which carries out processes like dispersed cosine conversion, movement compensation and movement detection, and a processor core that controls the dedicated circuits.

The MeP module combines a customizable MeP core and circuit cores for functional extension. The extension cores permit decoding of both image and voice signals.

Toshiba has developed a customizable, reusable processor core, called the media-embedded processor (MeP) core, that can be combined with dedicated circuit cores, connected by on-chip buses, to form MeP modules.

The MeP core 32-bit RISC processor has a five-stage pipeline configuration. Prior to synthesis, the following specifications can be defined: 1) the addition of optional commands (32-bit multiplication and division, zero detection, calculation of the max/min values); 2) memory configuration (up to 16 Kbytes for command cache and data cache, up to 32 Kbytes for command RAM, and up to 128 Kbytes for data RAM); 3) debug support; 4) the number of channels for timer/counter; 5) the priority level for the cut-in controller; and 6) the width of the external bus (32- or 64-bit).

Compared with a 32-bit RISC processor with a five-stage pipeline configuration (with 8 Kbytes command cache and 4 Kbytes data cache), Toshiba’s processor core reduces chip surface area to 40%, cycle time to 80%, power consumption to 40% and code sizes to about 60% for 32-bit devices.

Toshiba has already developed several circuit cores for functional extension, which can be combined with the MeP core. These include a coprocessor for image recognition, an audio DSP and an MPEG2 decoding circuit.

An automatic RTL text generation tool for the MeP core is provided, along with a software development environment. By entering data to define the MeP core and other circuits, development tools for compilers, assemblers, linkers, debuggers, and simulators are automatically generated, along with RTL texts.

Toshiba’s device will be available as an ASIC. The company is working with a third party to develop software development tools, in-circuit emulators compliant with JTAG, and evaluation boards, which are expected to be available by the end of the year.


Toshiba Semiconductor Company
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www.toshiba.com