Valid truths about chip design

CS. Muralidharan, the 33-year-old design manager at Software & Silicon Systems in Bangalore, is modest about his own accomplishments. Today’s complex chip designs are not the result of individual genius, he says, but the combination of many peoples’ expertise. “Each part of the design flow has become quite specialized,” he explains. “A designer will probably be exposed to most areas, but be an expert in one or two areas of the design flow.”


Muralidharan’s key technical strengths are in architecture and pre-silicon and post-silicon debugging. “I love the architecture phase of the design,” he says. “This is the phase which tests your creative abilities.” He has also demonstrated his abilities as an effective team leader. Creativity, adaptability, and leadership are the qualities that have driven his career.

The 33-year-old designer has an ME in electronics and communications engineering from the Indian Institute of Science in Bangalore. His core competence was mathematical modeling, with a focus on communications systems, and his first job was with the Centre for Development of Telematics (C-DOT) set up by the Indian government to design telecom switches.


At C-DOT Muralidharan was one of two engineers to design a Dual E1 Digital Trunk Interface ASIC, to implement the remote switching units (RSUs) feature of C-DOT’s switches. It included all the circuitry for interfacing to an E1 trunk: clock recovery, framer, and system synchronization logic. “This ASIC integrated the functionality of almost eight Dallas Semiconductor chips into one,” recalls Muralidharan. The design was executed on NEC’s 1.0 micron process, and was a first-time silicon success by 1995. The design is still in production. At C-DOT, Muralidharan also architected and designed other ASICs for communications applications.

By 1997, Indian IC design had picked up in the private sector, and Muralidharan quit C-DOT to join Software & Silicon Systems, which was then a design center of S3 Inc. In his new job, Muralidharan was involved in the validation and integration of a RISC core, designed in Bangalore, with an audio chip designed by S3 in the US. After S3 divested itself of Software & Silicon Systems, the company started working on networking chips for Level One, an Intel company. Packet switching was a new challenge, but Muralidharan, who was put in charge of validation and static timing analysis for the IXE2412 chip designed by Level One, rose to the occasion.

By the time Software & Silicon Systems was acquired by Intel, in February 2000, Muralidharan was already the technical head of the 25-member team that designed the IXE2424, a single-chip switch with over 25 million transistors that supports 24-port 10/100 and 4-port Gigabit Ethernet, with support for Layer 2, 3, and 4 switching and routing. The project called for the addition of two more ports to the IXE2412, and required significant redesign of the chip. Muralidharan’s team implemented new features that included MPLS (Multiprotocol Label Switching), Diffserv (Differentiated Services), and WRED (Weighted Random Early Detection).



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C.S. Muralidharan can be reached at Software & Silicon Systems
Tel: (91) 80-555-0888
Email: murali.chilukoor@intel.com