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| ( 01 Nov 2002 ) |
| By N.S. Manjunath, Editor |
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There has been a dramatic shift in the ASIC-design landscape. This is due to a manifold increase in FPGA technology, both in terms of gate capacity and flexibility in deploying FPGAs in system applications. ASIC-based designs, once touted as the best bet for the rapid consumerization of applications, are proving to be very costly when you factor in time-to-market issues. The risk of ASIC failure has made FPGAs the top choice for designers in prototype development.
Having multi-million-gate FPGAs at your disposal is one thing, but using them to your advantage is another matter. Help is on the way, however. There have been some revolutionary changes in system-level design methodologies, and the skill-set required to use these tools has been lowered as well. For example, traditionally you needed to be a hardware engineer with strong HDL coding skills to be able to describe the timing and structural details of your design. But in system-level designs you don’t need to worry about details in the beginning. With the advent of C-based languages, you can now implement algorithms and functions for system-level designs in FPGAs. Using C you can code algorithms that would be too complex to be coded in HDL and too slow to run on a CPU to be implemented in an FPGA. This means you can quickly perform design trade-offs at a higher level of design abstraction. In doing so, you keep the focus on optimizing your design to implement a new product concept and prototype it very quickly.
There are several reconfigurable development boards available today. Celoxica’s RC100 is a good example of a reconfigurable-logic development system. The RC100 consists of a 200K-gate Xilinx Spartan FPGA, several megabytes of flash RAM, a video decoder, PS/2 ports (for PC mouse/keyboard access), a parallel port interface, and a power supply adaptor. With the RC100 and Celoxica’s Handel C support package you can perform FPGA prototyping. Handel C and related tools let you rapidly port designs from prototype platform to the final system, or perform design reuse from one product to the next. Using this approach could reduce porting time by a factor of ten. There are several new solutions under development to simplify use of CPUs and FPGAs in reconfigurable computing designs. No doubt these initiatives will reduce time to market and promote quicker design prototyping.
So what about a reconfigurable-logic PC standard? Makers of FPGAs and vendors of EDA tools should collaborate to define a hardware platform for a reconfigurable-logic PC. Naturally this would require a well-defined API, contributed by leading embedded software companies. Appropriate test and debug interfaces would be necessary, which would necessitate the participation of instrument makers. Regarding the feasibility of this concept, I spoke with B.P. Suresh, an experienced design engineer who is now Business Director, Pac Rim, for Celoxica. Suresh thinks that the reconfigurable platform could appear in different versions. One could simply be a PCI bus-based add-on card with all the convenience and ease of use offered by the PC as a development platform. Owing to PCI-bus bandwidth limitations, there could be other approaches as well. If these design challenges are overcome, Suresh believes we could be seeing FPGA sockets on PC motherboards.
A pleasant side effect of this reconfigurable-logic design movement would be that the electronics hobbyist could make a comeback. In these days of dense device packages, soldering-iron-wielding enthusiasts have had little to play with. A reconfigurable-logic PC would offer the ‘new age’ electronics hobbyist a chance to showcase his creativity.
Send me your comments at nsmanjunath@rbi-asia.com.hk |
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