Cadence Enables Global Unichip to Complete Taiwan's First 65-NM Chip Design
(Interviews, 14 Mar 2007 )
Cadence Design Systems, Inc. has said that Global Unichip Corporation is the first Taiwan-based design company to complete a successful tapeout of a 65-nanometer device. The success of this 65-nanometer tapeout further strengthened GUC's advanced technology capabilities to serve the top tier customers worldwide.
"Targeting a 65-nanometer process technology is the state-of-the-art in semiconductor design," said Jim Lai, president and COO of GUC. "Success requires a tightly integrated design environment and an automated low-power design methodology. With comprehensive know-how of advanced technology designs, GUC used the combination of the Cadence Low-Power Solution and Encounter platform to build this low power design with over ten-million gates and implement it within seven weeks, which in turn helps GUC's customer to achieve a significant time-to-market advantage."
"We congratulate GUC on this achievement," said Chi-Ping Hsu, corporate vice president, IC Digital and Power Forward at Cadence. "GUC has clearly demonstrated a leading-edge design and implementation capability that targets advanced processes with state-of-the-art, low-power design techniques, and we are honored to have been part of it."
