Sequence Design is unveiling the EDA industry's most comprehensive suite of tools for power-aware design at this year's DAC with its Design For Power (DFP) Flow, attacking the challenges of low-power design holistically, from RTL to GDS. Customers already employing Sequence's DFP Flow are reporting RTL power reduction of up to 50 percent, a 50 percent speedup in design closure times, and leakage power reduction of up to 1,000X.
Demos of all Sequence products and their implementation in a complete DFP Flow will be available at DAC by advance registration. To register online: http://www.sequencedesign.com/dac-2007/index.htm.
"DFP is a holistic approach to power, enabling power exploration from the architectural level through physical implementation, reducing power while preventing power problems in timing, SI, and power grid design, with exclusive 'silicon-aware' features," said Vic Kulkarni, Sequence President and CEO.
