Free Print Subscription Printer-friendly version Email to a Friend

Azuro's PowerCentric Adopted by NVIDIA

(Interviews, 01 Jun 2007 )

Azuro Inc., a provider of advanced clock implementation tools for nanometer (nm) chip design, has announced that NVIDIA Corp. has entered into a multi-year agreement to purchase Azuro's PowerCentric. NVIDIA selected PowerCentric after a successful evaluation that demonstrated PowerCentric's ability to reduce power and also meet complex variability-driven clock tree implementation requirements.

"For NVIDIA, we must deliver unmatched features and performance in our graphics, multi-media communication processors and application processors while meeting tight power budgets, performance and area constraints. Consequently, our designs contain extremely complex clock trees with multiple branches at the block level that also needs to be balanced for min/max corners," said David Dumoulin, director of engineering at NVIDIA. "PowerCentric gives us the ability to implement superior clock trees inside our existing physical framework of EDA tools."

Azuro's PowerCentric is a clock tree synthesis and optimization solution that brings together unique algorithms for clock tree buffering, gate-level clock gate logic synthesis, and statistical average-case dynamic power analysis, to deliver a completely unified clock implementation solution for advanced nanometer designs. PowerCentric delivers 15-25 percent power savings above and beyond traditional EDA flows and also supports concurrent multi-corner clock tree balancing and timing optimization.

"Designers spend a lot of time getting their clock implementation right, especially within challenging nanometer environments that demand low power, high speed, and high yields all at the same time," said Ashutosh Mauskar, vice president of product marketing for Azuro. "PowerCentric implements clock gating and clock buffering entirely within one unified step, operating at the placed-gates level in the design flow. This enables PowerCentric to explore a larger global solution space of clock gating topologies and make better power-timing-variability trade-offs than other industry solutions. We are very excited to be working with NVIDIA at the cutting edge of nanometer ASIC design."

Azuro

 
Free Print Subscription Printer-friendly version Email to a Friend
 
Article Rating 
Average Rate: No rating yet
 
Poor Quite Good Good Very Good Excellent
 
Related Content 
 
 
KNOWLEDGE CENTER
Panasonic Key Devices Guide 2008 :
 
Fairchild Semiconductor :
 
Texas Instruments: DaVinci™ Technology
 
Texas Instruments: Safe Bet Series
 
 
 
Highest Rated  
Feedback Loop  

ADS BY GOOGLE 
 
 
 
ADVERTISEMENT
Press Release 
 
TECHNOLOGY NEWS
 
RESOURCE CENTER

 
 
PRODUCT NEWS
 
FEATURED SPONSORS
 
 
DESIGN CENTERS
 
ADVERTISEMENT
     
Reference Designs 
   
     
 
 
 


 
 
RSS
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   

POLL
What type of environmental regulation do you think will be most beneficial for the tech industry?
Proper recycling and disposal
Push for power efficiency and energy conservation
Chemical/lead regulation
View results