Aldec Inc. has released the new advanced Verilog linting engine—ALINT—that complies with the second edition of the Semiconductor Technology Academic Research Center (STARC) "RTL Design Style Guide." ALINT supports rules that cover various levels of RTL design cycle: from simple coding style rules and use of language constructs to complex constraints in synthesis and DFT areas. The new linting engine from Aldec provides flexible configuration features that allow companies to control implementation of corporate design guidelines.
ALINT automatically extracts the synthesizable subset of Verilog code and performs checks against the use of improper constructs for synthesis, incompletely specified conditional statements, potential problems with resource sharing in the synthesized netlist, simulation/synthesis mismatches, such as incomplete sensitivity lists or functions, mistakes with multiple assignments to the same signal.
A built-in synthesis emulation framework automatically converts extracted RTL to the Verilog netlist model and allows detection of unwanted latches and flip-flops with fixed values on the inputs, detection of problems with asynchronous controls of inferred flip-flops and issues with inferences of tri-state buffers.
ALINT is also capable of performing the checks at the chip netlist level by analyzing the netlist model of the whole chip. Analyzing the whole chip allows for the monitoring of typical DFT problems, such as the influence of global clock signals on non-clocking ports, uncontrollability of clocks, unwanted synchronous feedbacks and unwanted direct connections of flip-flop/latch outputs to control lines of other storage elements.
