Ramp discharge fall time control, or how to set maximum duty cycle

Many PWM controllers on the market today have internal clocks that consist of a circuit that charges a capacitor to a preset voltage, then rapidly discharges the ramp when it reaches that voltage. The cycle then repeats itself. This provides a saw-tooth ramp voltage that repeats setting up a frequency used to control the cyclic switching of the power field effect transistor or FET.

In the case of voltage mode control, the ramp’s voltage is used by the pulse width comparator to set a pulse width. Additionally, in the case of current mode control, a portion of the ramp can be added to the current ramp to provide added stability to the system.

Generally, the power switches are off when the converters discharge the ramp (fall or off time). By controlling this fall time, the maximum duty cycle of the converter can be fixed. This paper discusses available options for this “off time.” It also addresses the effect of the tolerances of various components on this fall time, and other circuit parameters. For this discussion we need the characteristics of a controller IC, so we chose the UCC38C42. The results of this theoretical analysis are compared to a breadboard circuit to verify the calculation against real results.

From the data sheet, we know the discharge current is typically 8.4 mA. Suppose that we want a 200 kHz operation with a maximum pulse width of 75 percent. From this, we can calculate the total charge that is going through the discharge transistor.

This yields a total charge of:

Now, the method of charging the capacitor with this IC is a resistor from Vref to the time capacitor (Ct) pin of the IC. This means that during the entire switching cycle there will be a current from Vref to the Ct pin. That current is a function of the voltage on the Ct pin and the value of the resistor Rt.

Also from the spec sheet, we know that the voltage on the Ct will change by 1.9 volts. Though it is not perfectly linear, it is very close to a straight line, as the voltage across the Rt is only changed by .4 of the source voltage and it will start near ground and discharge to near ground.

Looking at Figure 1, the positive slope represents the charging voltage of the capacitor. The area under the slope represents the accumulated charge on the capacitor in 75 percent of the cycle. Since the voltage falls in a straight line, the current through the resistor during this time is the same as during the rise time at each corresponding voltage. Therefore, the accumulated current through the Rt during the discharge time amounts to one-third of the charge on the Ct during the charge time.

The total charge through the internal discharge transistor becomes both the charge on the capacitor at the time the discharge is initiated, and the current through Rt during the time the capacitor is being discharged. This total charge is equal to the peak charge on the capacitor, plus an additional one-third that flows through the resistor during the discharge of the capacitor for a total of one and one-third of the capacitor’s peak charge. We know this because the discharge ramp is also a straight line. So effectively the charge current will be very similar to the charge current over time. Therefore, since the charging current is present for three-fourths of the time, and the discharge current is there for one-fourth of the time, the accumulated charge during the discharge portion will be one-third of that during the charge time.

From this we can determine the value of Ct. We know that the voltage change on the capacitor is 1.9 volts. We also know that the change in charge on the capacitor at the time the voltage is at its peak is (10.5 nC * (3/4)) or 7.875nC.

This defines the capacitor as (7.875 nC/1.9 V) or 4.145 nF. Now that we have the capacitance defined, we can define the resistor. The voltage source is 5 volts and from the equation:

We solve for Rt using the two known voltages of 1.9 volts for the change in value of V and 5.0 volts for Vref, and 3.75 µs for the time in the equation:.

This yields a Rt of 1.893 kΩ. The results of this analysis were then tested in the simulator. The voltage on the capacitor is shown in Figure 2.

As can be seen in Figure 2, both trace slopes are very close to linear. The current waveform through the resistor shows a mirrored yet similar result.

The sharp upward waveform corresponds to the discharge of the capacitor, while the slow decrease in the current is charging the capacitor.

Next, the effects of tolerances are examined. Both the high- and low- trip-points have slight variations in voltage.

A higher voltage for the trip-point results in a longer charge and discharge time. This causes a change to the operation by slowing the converters switching frequency, but the maximum duty cycle remains the same percentage of the cycle because the slopes of the charge and discharge retain the same shape.

Similarly, a lower trip-point causes the frequency to increase because the voltage on Ct reaches the lower trip-point faster.

As a result of tolerances, variations in the capacitor value have the same effect as the variations in the trip-points. The ratio of maximum pulse width to total cycle time stays the same. Basically this is due to the linear nature of the charge and discharge cycle.

The effect of variation on the discharge current changes the ratio of time to charge or discharge the capacitor. If the discharge current is lower than is typical, the discharge time is longer but the charge time stays the same. This has two effects. First, it decreases the frequency. Second, it decreases the available maximum duty cycle by increasing the ratio of the “off” time to the “ON” time.

If the discharge current is higher than is typical, the reverse happens. If the circuit relies on a preset maximum duty cycle to operate, care must be taken to ensure that, should the discharge current be at a maximum, the circuit can still operate within safe limits. The same care must be taken with tolerances on the Rt used. Usually this is a small number compared to the variations in the discharge current as 0.1 percent resistors are commonly recommended.

In this IC, the variations of discharge current are from 7.2 mA to 9.5 mA. Given that the current could be at the maximum, and it is essential that the duty cycle never exceed the 75 percent limit, the circuit should be designed with that in mind. The worst-case condition would be the 9.5 mA discharge current. This would shift the Ct to 4.688 nF and Rt to 1.631 kΩ.

Naturally, if the discharge current is at the other extreme of 7.2 mA, the maximum duty cycle will be less than the desired 75 percent, and the frequency will be slower than the desired 200 kHz.

We can calculate the maximum duty cycle at the minimum discharge current. Since the charge on the capacitor is achieved in 3.75 us, and the capacitor is 4.688 nF, this equates to an average current of Iavg over the charge cycle.

This will be the same average current through the resistor during the discharge time. The difference between the discharge current of 7.2 mA and the average current through the resistor (Iavg) is the average current available to discharge the capacitor.

Using Equation 5, we can calculate the time needed to discharge the capacitor.


When these equations are solved, the discharge time is 1.846 μs. This means that the maximum duty cycle for the lower discharge current will be 67 percent, and a reduced frequency of 178.7 kHz. The circuit was simulated with the following results:

Next, the circuit designer must determine from the specification if the Ct and Rt ranges are within the operating range of the IC. He also must verify that the frequency variations from 178 kHz to 200 kHz with a maximum duty varying from 67 percent at the low frequency to 75 percent at the 200 kHz frequency will work in the application.

If the circuit must work at 200 kHz or better, it should be synchronized by applying a voltage pulse between the ground and the Ct capacitor for a time that is less than the fall time. This causes the discharge circuit in the IC to trip, discharging the capacitor. However, the maximum duty ratio at the 200 kHz operation will be the same as it would be if the circuit had not been tripped. If the circuit is free-running at 178 kHz and 67 percent duty cycle, then with synchronization it will run at 200 kHz. But it still has a 67 percent max duty cycle. The amplitude of the ramp waveform is reduced.

A breadboard was built with the measured value of Ct as 4.31 nF and Rt was 1.8 kΩ. The calculations determine that the frequency should be 192 kHz with that capacitance, and that was the measured value. See Figure 6.

The duty cycle was slightly off at about 77 percent. This could be measurement error. Figure 7 measures the off time, which corresponds to the down slope.

The analysis, simulations and actual measurements all show a good correlation.

References:
For more information, visit www.ti.com/sc/device/UCC38C42.

About the Author
John Bottrill is a Senior Applications Engineer at Texas Instruments, Manchester, NH, where he provides support to customers and evaluates new ICs before release. He received two patents and has written many articles on similar topics. He received his B. Sc. in Electrical Engineering in 1973 from Queen’s University at Kingston, Ontario, Canada.

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