Design Feature: What system designers need to know about deep-submicron ASICs

Exploiting the full speed and complexity of deep-submicron ASICs requires knowledge of how IC physics is changing, what the resulting implications are for ASIC design tools, and how to select design tools that let you create functional deep-submicron ASICs. The steps for getting any semiconductor product to market are the same: Develop a Spice model library for the basic devices, develop a cell library, design a chip, and insert the chip into a system. Depending on your responsibilities as a system designer, you may need to perform one or more of the last three steps. Usually, the ASIC vendor develops the Spice model libraries that describe the fundamental capabilities of the fabrication process. From these fundamentals, either you or the ASIC vendor develops the logic cells that you use to develop the various logic functions of your ASIC. Assuming everything goes well, the completed ASIC performs the desired function when you drop it into your system.

The changed physics of deep-submicron silicon structures is creating a significant discontinuity in ASIC performance as device geometries drop below 0.5µm. Figure 1 illustrates a typical structured-custom IC, comprising several different blocks. You may encounter a number of performance problems with these blocks. High-performance data paths require high-speed data buses and often employ timing-sensitive dynamic logic for optimum speed. RAMs contain large numbers of transistors, so they generally require the smallest transistors that the process can fabricate. Random logic blocks require complex cell libraries and often contain intricate wire routing with complex delays. Analog blocks and PLLs rely on predictable analog transistor behavior.

REAL TRANSISTOR PERFORMANCE
In each of these examples, problems arise when the ASIC design tool incorrectly models real transistor performance. As device geometries shrink below 0.5µm, accurate modeling of transistor switching, power consumption, and the relationship between a gate and the associated interconnect becomes complex. The modeling problems stem from a breakdown in the overly simplistic models that describe the analog operation of the deep-submicron silicon structures. Some ASIC vendors have attempted to create deep-submicron Spice models by scaling existing submicron models. Models that vendors have scaled from submicron to deep-submicron IC process technology don’t accurately reflect real silicon performance.

ASIC and design-tool vendors have resorted to putting an increasing amount of “fudge” in their deep-submicron specification sheets and timing tools to account for the increasing inaccuracy of the fundamental device models. Designers have actually seen delay errors of 70% between simulations and actual deep-submicron silicon performance. You can design deep-submicron ASICs this way, but you cannot achieve either the full speed that is possible from deep-submicron fabrication processes or the kind of gate densities you’d expect. You often end up in serious finger-pointing arguments with your ASIC and design-tool vendors when ASICs fail to perform at expected speeds. However, you do not have to settle for reduced performance or inefficient silicon usage. Proper modeling of the deep-submicron devices allows you to take full advantage of the silicon’s underlying performance.

Deep-submicron physics mostly affects the Spice-level models. Transistor physics no longer maps neatly into the traditional Spice transistor equations for several reasons. First, the devices are finally starting to operate near their physical limits. Consider a deep-submicron FET built with an oxide thickness of 60. With 3V applied between the gate and the source or drain, the oxide experiences an electric field of 5MV/cm, which is very close to the oxide’s breakdown voltage.
At these field strengths, second-order effects, such as impact ionization, drain-induced barrier lowering, and channel-length modulation, play an increasingly important role. Previously, Spice modeling for ASIC transistors ignored these second-order effects because they weren’t
needed for accurate modeling. Spice modeling for deep-submicron transistors must take these effects into account.

SHRINKING TRANSISTORS
The second reason that Spice models must change is because the performance variance for transistors fabricated with different-sized geometries is quite large (Figure 2). With 0.35µm geometries, transistor drain-to-source currents (IDS) can vary ±30% from device to device on the same chip. You can see considerable lot-to-lot variation. So, IDS predictability is decreasing as device geometries decrease. IDS affects switching time and power dissipation.

Third, wire geometries aren’t scaling with transistor geometries; the transistors are shrinking a lot faster than the wires. Consequently, the wires’ resistance and capacitance are not scaling with transistor switching speeds. In fact, average wire lengths on ASICs are increasing as ASICs get larger and more complex so that wire (or interconnect) delays now dominate over gate delays. ASIC delay calculators do not properly account for wire delays. Some vendors have made linear tweaks to their submicron ASIC design tools, expecting that linear scaling can account properly for the delays at the deep-submicron level. Linear scaling can’t properly model deep-submicron wire delays.

Because of these fundamental changes in device physics for deep-submicron ASICs, the HDL-to-silicon design flow of submicron ASIC design tools cracks. These existing design tools assume that wires on the ASIC behave the same whether they are short or long and logic devices can be treated as black boxes with unvarying performance.

The deep-submicron reality is quite different. Extremely small transistors exhibit irregular behavior. They have input-slope, load, and temperature sensitivities that design tools have never before needed to model. Further, the smaller operating voltages of deep-submicron ASICs mean that transistors must operate with a smaller transition region. The effects of a smaller transition region are evident in sensitivities to output loading and the slope of the input signal. These factors determine transistor switching speed, power consumption, and temperature. Deep-submicron transistors exhibit more sensitivity to temperature than larger devices; switching time can vary as much as ±15% due to thermal effects. In addition, although the output load of the interconnect wire in deep-submicron ASICs still looks linear because the wire has an RC impedance, the effects of the load are nonlinear because the output load affects the transistor’s slew-rate sensitivity.

GET ALL THE PERFORMANCE YOU BUY
As the system designer, you probably have not had to deal with transistor-level effects above the submicron domain. You designed the ASIC’s logic and handed the netlist to the ASIC vendor for placement and routing. Because the cell libraries were based on approximations that did a fairly good job of modeling transistor behavior, you could get by without knowing the analog nature of the fundamental devices. However, if you want to get your money’s worth from deep-submicron fabrication processes, you must at least ask the right questions of the deep-submicron ASIC vendor to ensure that the design-tool models accurately reflect the underlying physics of the silicon.

Here are the questions to ask the deep-submicron ASIC vendor:
· Are you giving me accurate models? How do you ensure that your Spice models work over your process range? How can you provide the model parameters for your process? What performance do you guarantee?

Here are the items you need from your deep-submicron ASIC tool vendor:

· A feedback loop from the physical-design stage that provides more than just loads. More complex device-modeling libraries. A wire-model library.

COMPETING APPROACHES
There are currently three competing approaches to building a deep-submicron wire-model library: look-up tables, piecewise-linear approximations, and polynomial equations. All three approaches work, but, unfortunately, not all ASIC or design tool vendors support all types of models. You could find yourself in a spotty mix-and-match situation. Ineffective or incomplete empirical modeling of interconnect delays further complicates the situation. Most ASIC-process test chips use simple ring oscillators with first- or second-layer metal routing. Few contain the complex wire routings needed to measure actual deep-submicron wire delays. In reality, the ASIC industry must still resolve these wire-modeling and behavior-extraction problems for deep-submicron products.

Ultimately, deep-submicron ASICs put the system designer at a crossroads. If you’re not exploiting the full capabilities of the deep-submicron process, you can probably continue to design as you have in the past. However, if you want to realize the full potential of deep-submicron technology and get the performance and complexity you pay for when you buy deep-submicron ASICs, then you’d better examine your ASIC and ASIC tool vendors more closely than you ever have before.


AUTHOR INFORMATION
Isadore Katz was the vice-president of marketing at Meta-Software. He has served as the vice-president of marketing at Cadence’s IC Design Division and has held senior positions at Daisy Systems and EDA Systems. He has been a senior industry analyst at Dataquest.

Captions
Figure 1: Structured custom ICs comprise several blocks—each with potential problems with deep-micron processes. High-performace data paths require high-speed data buses and often employ timing-sensitive dynamic logic. RAMs generally require the smallest transistors that the process can fabricate. Random logic blocks require complex cell libraries and intricate wire routing with complex delays. Analog blocks and PLLs rely on predictable analog transistor behavior.

Figure 2: The performance variance for transistors fabricated with different-sized geometries is quite large, and can be as much as 60% (±30%) for deep-submicron processes.

Click here for Illustrations:

Figure 1

Figure 2