Altera extends productivity advantage with Quartus II Software Version 7.2

Delivering top productivity tools for FPGA users, Altera Corporation (NASDAQ: ALTR) has announced its Quartus II software version 7.2. With this new software version, Altera continues to extend its advantage in compile times, a key productivity metric. Designers using Quartus II software version 7.2 can expect their Stratix III FPGAs compile-time advantage to grow to three times that of competing high-end 65-nm FPGAs.

“More than 15 years experience using the largest and most complex FPGAs from multiple vendors has taught me that Altera's Quartus II software is the productivity winner,” said Joe Jacob, president of Quasar Systems, a design services company. "Using Altera's Quartus II software tool suite, I was able to build and test a PCI Master/Target system with DMA and memory interfaces in a single day that would have taken four to six weeks using competitive tools. The Quartus II software enables me to finish my designs quicker than other tool suites.”

“Our customers today are increasingly concerned about designer productivity, so they look for tools that give them a competitive edge,” said Louie Leung, marketing director at Altera. “With our latest Quartus II software, our productivity advantage has improved from 2X to 3X compared to our competitor’s solutions, enabling our customers to compile their designs faster and meet their aggressive time-to-market goals.”

Quartus II software version 7.2 includes productivity and performance-focused enhancements that enable designers to achieve faster compile times and meet performance requirements. A Quartus II software user working with a multiprocessor computer will experience, on average, a 20 percent reduction in compile times over single-processor computers. Additionally, enhanced place-and-route algorithms enable Stratix III customers to meet their high-performance requirements and offer a two speed grade advantage versus competitors. Stratix III customers interested in learning more about the benefits of using the Quartus II software can visit: www.altera.com/stratix3performance

Enhancements to Quartus II Version 7.2

· New Live I/O Checking – The addition of real-time pin-out validation allows faster verification of pin placement and assignments.
· Improved Avalon® Streaming Support in SOPC Builder – New automatic insertion of adapters makes finishing your Avalon Streaming designs quicker and easier. In addition, the revamped component editor includes a faster GUI for adding your custom components and support for Avalon Streaming.
· Expanded OS Support With Windows Vista – Altera is the only FPGA vendor to support both Windows Vista 32- and 64-bit editions with its Quartus II software.
· New State Machine Editor – Accelerate your design entry with a new graphical state machine design entry tool.
· Easier Chip Debug With Enhanced SignalTap® II – Improved trigger condition settings capture data based on a sequential set of events to allow for faster chip debug. In addition, Signal Tap II offers enhanced segmented acquisition for better use of the memory buffer, allowing for easier hardware verification.
· Faster Timing Closure With Enhanced TimeQuest – New clock-as-data feature enables designers to analyze timing when clock signals are used as data, a feature not available in most timing analysis tools. In addition, TimeQuest’s new waveform viewer enables designers to visualize timing relationships for faster timing closure.
· Simplified Software Download – Altera offers a new unified download and installation for Quartus II Subscription Edition on the Linux operating systems to support faster software upgrades.

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