Using flexible automotive FPGAs to increase on-chip system level integration and lower BOM costs

Automotive manufacturers continue to improve in-vehicle comfort, safety, convenience, productivity, and entertainment which, in turn, drives the use of diverse in-vehicle digital technologies. However, the long development cycles in automotive are very difficult to match with the latest technologies, especially with the constantly changing in-vehicle networking specifications, and the quickly emerging and disappearing technologies from the consumer market, resulting in high engineering costs and obsolescence. Add low cost targets, extended temperature ranges, high reliability and quality targets, and limited physical board space to the mix, and the challenges in automotive design are daunting at best. Programmable logic devices (PLDs), such as field-programmable gate arrays (FPGAs) and Complex PLDs (CPLDs), have appeared on the scene and are proving to be a flexible, cost effective and viable technical solution while offering better time-to-market than traditional hardware solutions currently being utilized.

Programmable logic devices (PLDs) like FPGAs and CPLDs provide the utmost in hardware flexibility. Due to their re-programmable nature, developers are offered the luxury of updating designs from prototype all the way through the production phase. Since PLD designs are programmed using a software bit stream, making quick design modifications are easy and straight forward, and there are no NRE or mask costs.

Since PLDs are scalable in both logic density and package migration, they allow designers to make whole-scale changes and still target to the correct pin and logic density. This leads to excellent price per logic cost points and specific tailored pin counts for each design. PLD designs are made up of hardware description language (HDL) to implement logic and C source files for embedded processors. These design source files can be used to target and reconfigure any PLD, any number of times. Designers may also leverage existing designs or take specific parts of designs for re-use in new projects. This scalability and re-use of code eliminates product obsolescence and can reduce costs because developers can quickly and easily upgrade their designs to target the latest low cost device.

A general misconception that we see in the automotive design community is the thinking that FPGAs are too expensive to take into production. Five years ago, one million system gates cost in the range of $45. Today, these same one million system gate devices are selling for under $10, with the smaller 100K system gate designs selling at under $3, allowing for massive integration of multiple components into a single device. It is now completely possible to take an FPGA into full production and achieve the system cost targets required by the automotive market.

The programmable nature of PLDs offers yet another level of advantage - in-vehicle programming and re-programming. Device in-vehicle programming enables algorithms and functions to be upgraded even after product deployment. Since current telematics and video image recognition systems are in the early stages of research and development, the ability to make in-field upgrades can be a crucial asset. As technology - such as image processing algorithms - improves over time, hardware upgrades can be accomplished in a matter of minutes without having to redesign an ASSP or layout a new board.

For example, in instrument cluster and center stack display designs, LVDS (low voltage differential signaling) transceivers have given automotive designers the low-noise, high-speed signaling interface needed to implement flat panel display (FPD) applications. Recently, RSDS (reduced swing differential signaling) signaling interfaces have been adopted by various display manufacturers. This new signaling technology comes with a number of benefits over LVDS, including lower dynamic power consumption, further reduction in radiated EMI, reduced bus widths, high noise rejection, and high throughput. Again, the dynamic nature of PLDs gives developers the choice advantage. PLDs support a multitude of I/O signaling standards, giving developers the option to incorporate newly adopted technologies, such as RSDS, into their design. By adapting quickly to changing standards and adopting the latest and greatest technologies, companies create the time-to-market advantage for themselves, guaranteeing a win over any competition.

On the reliability side of automotive design, there are many elements to consider. While ISO-TS16949 Certification is a given in the market, a designer needs to take a look a little bit deeper. Many companies are using third party subcontractors for their production. Designers must ensure the supplier itself is certified. If not, the supplier does not have its design and operational flows certified to the industry standard. In automotive telematics applications, AEC-Q100 automotive IC stress test qualifications and PPAP documentation is also mandatory.

Back on the technical side of things, using PLDs will also improve reliability. Although LVDS transmitter and receiver pairs are readily available on the market, employing PLDs allow developers to integrate the transceiver onto a single device. PLDs not only offer various integrated signaling capabilities, but they also integrate source and termination resistors. By eliminating the multitude of discrete components, the designer achieves a reduced component count, resulting in a simplified PCB and a far more reliable signaling structure. The end result is a more cost-effective and reliable system.

PLDs not only allow integration of signaling capabilities, they also provide the capability to contain an entire system on a single programmable device; including the processor. By placing an entire design on a single chip, designers can reduce the number of components on the board and their relative connections resulting in a scalable, portable, and reliable system. Color temperature, for instance, is one of the many image enhancement issues facing vehicular display developers. Different regions around the world require different color temperature preferences. By using a PLD to create a scalable solution for color temperature adjustment, this solution can be leveraged across multiple geographies to support multiple display types, with minor adjustments toward the geographically preferred color temperature setting. Platform scalability and design reliability stay intact, while taking advantage of cost savings.

Most PLDs have built-in clock conditioning for duty cycle correction and clock managers that allow clock manipulations. The clock managers are placed on internal dedicated, low-skew lines enabling precise, global clock signals. Such clocks enable a complete solution for high-speed clock designs, such as those needed for image processing. De-skewed internal and external clocks eliminate clock distribution delays and provide high-resolution phase-shifting. These clocks also have flexible frequency synthesis, generating clock frequencies equal to a fractional or integer multiple of the input clock frequency. Dependable clock management systems are useful for timing and control circuits to meet growing display requirements.

Image Scaling needs can also be addressed by PLDs. Take real-time image re-sizing, for example. The line buffers and coefficient banks can be implemented using block RAMs. Everything else including the vertical and horizontal multipliers, the adder tree, the sequencers and control, can be implemented using basic logic structures within the PLD. There is also no intermediate buffering necessary between the vertical and horizontal multipliers, therefore there is no frame latency.

Many automotive telematics applications today are demanding high-performance video and image processing. PLDs have a number of features that make them ideal for handling applications, such as navigation systems and rear-seat entertainment/video, and utilizing PLDs will offer various performance advantages purely from an architectural perspective. For example, distributed RAM on FPGAs are used to store DSP coefficients and FIR filters offering high memory bandwidth. Dual-port block RAMs are available for optimized data buffering and storage and for applications like FFTs. PLDs can also perform billions of MACs per second; using MACs built by embedded multipliers and accumulators. The large number of multipliers found in PLDs can also be used to create parallel multiplier arrays that support complex high-performance DSP tasks, where conventional DSPs are limited to serial processing. Embedded SRL16s, made up of registers and LUTs, enables highly efficient implementations of multi-channel data paths. They can also dramatically increase FPGA compute density by enabling the construction of efficient time division multiplexed (TDM) hardware structures.

Simply by using PLDs, developers can leverage its flexible architecture and take advantage of distributed DSP resources, such as look up tables (LUTs), registers, multipliers, and memory. With distributed DSP resources throughout the device, segmented routing, and component usage, FPGAs allow algorithms to be optimally implemented in the device. For example, designers can size an array to suit the exact calculation requirements, ideal for performing calculations on images. Calculations can be performed on clusters of pixels, such as discrete cosine transform (DCT) blocks concurrently with other blocks in the picture, instead of having to scan the entire picture sequentially. And because processing can now be done in real time, less memory is needed for buffering pixel values when using PLDs.

Although conventional programmable DSP can address a wide range of applications, it has its limitations. For instance, conventional DSPs are bound by their architecture, with fixed data widths and limited MAC units, therefore limiting its data throughput by using serial processing. This forces the system to operate at high clock frequencies to increase data throughput creating yet another set of challenges. At the same time, it takes multiple DSPs to meet bandwidth needs, creating power and board space issues. By using a PLD, a designer can implement the custom solutions required to address higher-performance, high quality, real-time display challenges. PLDs, with its flexible architecture and DSP resources, support both serial and parallel processing. By opting to use parallel processing, a system has the potential to maximize its data throughput with a single clock cycle. Again, the designer can size the array to suit specific processing needs.

In summary, today’s PLDs have become a viable alternative to fixed logic devices for the automotive industry. PLD suppliers are demonstrating their commitment to serving the automotive market by offering temperature-tolerant packaging of -40C to +125C, and striving to meet the stringent requirements of the automotive industry including ISO TS16949 certification, AEC-Q100 qualification flow and the Production Part Approval Process (PPAP). This allows automotive engineers to meet their challenging design goals with complete confidence in component quality and performance, while providing the ability to respond quickly to constantly changing automotive and multimedia standards and protocols.


Click here for Illustrations:

Figure 1