Xilinx accelerates development of SFI-5 applications with hardware-verified solutions

Xilinx has announced availability of a free hardware-verified reference design and 3rd party IP for the optical internetworking forum (OIF) SERDES framer interface level 5 (SFI-5) standard. The SFI-5 interface enables communication between the optical transmission devices and the network processing system.

Based on its 65nm Xilinx Virtex(TM)-5 LX330T FPGAs, the reference design accelerates the development of wired networking systems requiring 40Gbps payload rates, enabling applications using transport interfaces like OC768/STM256 and OTN OTU-3 in systems such as optical cross connects, fiber optics terminators and repeaters, 40G multiplexers, and test equipment.
The reference design has been hardware verified on the Xilinx ML525 evaluation platform and characterized for skew, temperature, process, and voltage variations to ensure reliable interface, compatible with the OIF SFI-5 standard.

Leveraging low power transceivers -- typically consuming less than 100mW per transmitter/receiver pair -- this Virtex-5 LXT FPGA-based reference design uses 17 transceivers (16 for data and one for calibration).

Wired networking designers seeking additional Virtex-5 LXT FPGA solutions for 40G system design can also benefit from IP offerings from Xilinx Alliance program participant Avalon Microelectronics for 40Gbps applications, including: SxI-5-compliant SFI-5 physical layer core, 40G SONET-768/SDH-256 core with POS and 43G OTU-3 with G.709 FEC or other Enhanced FEC.

Xilinx