STMicroelectronics achieves highest memory density for ARM9 standard MCUs, delivering pin- and function compatibility with embedded flash of 288 Kbytes to 2.1 Mbytes

STMicroelectronics has increased the on-chip Flash capacity of its STR91xFA ARM966E-S based MCU family by introducing 1.1 Mbyte and 2.1 Mbyte variants, delivering higher memory density than any other ARM9, or ARM7-TDMI, based standard MCU currently available. The new devices are pin- and function compatible with existing 288 Kbyte and 544 Kbyte versions in LQFP-80, LQFP-128 and BGA-144 packages, allowing engineers to scale designs easily without incurring expensive changes to their circuit boards.

As the first family to combine the ARM966E-S CPU core with Ethernet connectivity and large memory capacity including 96 Kbytes of SRAM, the STR91xFA series now further extends the performance of networked embeddable systems such as web servers, printer controllers and other applications that require large amounts of code or data storage. These applications also include Point-of-Sale terminals and peripherals, factory-automation equipment, serial-protocol gateways, security and surveillance equipment and building-automation systems.

The 1.1 Mbyte STR91xFAx46 and 2.1 Mbyte STR91xFAx47 enable engineers to build more complex embedded functionality using on-chip memory, thereby adding security against piracy, saving board space as well as bill-of-materials costs. With integrated Ethernet, USB, and CAN interfaces, as well as a 10-bit ADC, multiple timers and up to 80 5V-tolerant general-purpose I/Os, the STR910xFA delivers a single-chip solution capable of transforming embedded-control applications into low-cost nodes on a local network, or on the Internet.

Designers using the new STR91x devices in Ethernet-based solutions can also take advantage of the royalty-free TCP/IP stack recently announced by ST, which accelerates application development while occupying a footprint of less than 12 Kbyte of memory.

The ARM966E-S CPU core at the heart of the STR91x family achieves 96 MIPS peak performance at 96 MHz, by introducing several performance enhancements over the ARM7TDMI architecture. These include separate internal busses to high-speed burst Flash memory and zero-latency SRAM, each attached efficiently to the core through a highly optimized Tightly-Coupled Memory (TCM) interface for rapid access. In addition, the ARM966E-S core supports single-cycle Digital Signal Processing (DSP) instructions, enabling the STR910F to satisfy both control and signal-processing requirements and delivering clear advantages over traditional solutions based on separate DSP and control processors.

STMicroelectronics