Azuro announced that Atheros Communications has successfully produced working silicon on an advanced single chip Bluetooth 2.1 + EDR design for high-performance mobile and embedded wireless products using Azuro’s PowerCentric.
Atheros’ design was already aggressively clock gated using front-end RTL synthesis tools in addition to containing multiple levels of hand-crafted clock gating logic. By utilizing PowerCentric, Atheros was able to generate superior quality clock trees, reduce post-CTS design flow iterations, and achieve 20% reduction in total chip power consumption without any impact on chip size or performance.
“Clock tree synthesis is a critical step in the design flow which the EDA industry has under-invested in for some time now,” said Steve Padnos, Methodology Architect for Atheros. “Azuro's PowerCentric truly is a fresh approach to CTS, and enables us to deliver silicon to market faster and with even lower power consumption than before.”
Azuro's PowerCentric is a complete replacement for CTS and post-CTS optimization. Unlike traditional CTS solutions, PowerCentric's unique multi-objective algorithm directly considers power, congestion, and timing across multiple modes and corners during the clock tree buffering process. By combining this multi-objective algorithm with advanced logic path timing and placement optimization methods, PowerCentric is able to deliver ultra-low power clock structures without impacting design speed or area, even for the most complex SoC designs.
