Designing with QDRII+ and QDRII in one system

Memory devices are evolving to match the needs of applications that are in continuous demand, such as high-performance communications, networking, and DSP systems. Specialized memory products that optimize some architectures’ memory bandwidth have successfully increased the overall performance in a variety of data-processing systems, and operating speeds have increased to as much as 500 MHz. To meet the demand for these products, the QDR (quad-data-rate) Consortium, which comprises Cypress, IDT, NEC Electronics, Renesas, and Samsung (www.cypress.com, www.idt.com, www.nec.com, www.renesas.com, www.samsung.com), has released the next generation of SRAMs. The QDRII+ (quad-data-rate II+) SRAMs meet these requirements by offering higher memory bandwidth, improved timing margins, and more flexibility in system designs. QDRII+ SRAMs offer 50% higher speeds than QDRII SRAMs, deliver a bandwidth as high as 72 Gbps, and come in FBGA packages. The QDRII+ architecture uses the currently installed infrastructure to create higher performing products and allows a direct transition to higher frequencies.

QDRII and QDRII+ devices have two independently operating ports that run at twice the selected clock rate, allowing a transfer of four data words across the two ports in a single clock cycle. QDRII and QDRII+-SRAM devices provide concurrent reads and writes, allowing simultaneous access to the same address location. This innovative architecture provides four-times-better performance than other SRAM devices in networking applications. These devices suit bandwidth-intensive, low-latency applications, such as controller-buffer memory, statistics memory, look-up tables, and linked lists.

QDRII and QDRII+-SRAM overview
QDRII and QDRII+ SRAM can perform two data writes and two data reads per clock cycle. They use one port, D, for writing data and another port, Q, for reading data (see box “QDRII- and QDRII+-interface signals”). These unidirectional data ports support simultaneous reads and writes and allow back-to-back transactions without the contention issues that can occur when using a bidirectional data bus. Write and read operations share the address ports. QDRII and QDRII+-SRAM devices use input clocks K and K# to control the input signals, output clocks C and C# to control the output data bus only in QDRII SRAMs, and source-synchronous echo clocks CQ and CQ#.

The architecture supports burst-oriented write and read operations, and all the data-bus-width configurations support burst lengths of two and four. Both burst-of-two and burst-of-four QDRII- and QDRII+-SRAM devices provide the same overall bandwidth at a given clock speed. QDRII-SRAM devices use either the 1.5 or the 1.8V HSTL (high-speed-transistor-logic) Class I I/O standard, whereas QDRII+-SRAM devices use only the 1.5V HSTL Class I I/O standard. QDRII- and QDRII+-SRAM devices use an internal DLL (delay-locked loop) to align the data’s edge with the input clocks. You can optionally turn off the DLL, but doing so degrades the performance of the QDRII and QDRII+-SRAM devices. All timing analyses in this article assume that the DLL is on. QDRII- and QDRII+-SRAM devices also offer programmable-impedance output buffers. You program the output buffers by terminating the ZQ pin to VSS through resistor RQ. The value of RQ should be five times the desired output impedance—175 to 350Ω—with a tolerance of 15%.

QDRII+-SRAM features
QDRII+-SRAM architectures typically find use in high-performance networking and communication applications supporting frequencies as high as 500 MHz. The designers of this new communications-memory standard developed it for network switches, routers, and other communications applications. The QDRII+-SRAM devices extend the QDRII family of SRAMs in frequency and performance. The QDRII+ SRAM devices function similarly to a QDRII SRAM but have slight differences in the timing. However, because they have similar performance, you can use them interchangeably with only a few changes to the memory controller and the board, depending on the application. Designing the system to accommodate both QDRII and QDRII+ paves the way for higher performance in the QDRII designs.

Design changes for QDRII and QDRII+
QDRII and the QDRII+ SRAMs differ in ac and dc parameters due to the higher speeds of operation in QDRII+. The major differences are that QDRII+ has a higher read latency, has no C or C# clocks, employs a QVLD (output-valid-indicator) pin, uses slightly different pinouts, and has different timing parameters. Higher read latency enables higher frequency operations. Hence, the design should support speeds to 500 MHz, and you should terminate the data signals. The QDRII has a read latency of 1.5 clock cycles, whereas the QDRII+ supports both 2- and 2.5-clock-cycle read latencies. The memory controller should support either 2 or 2.5 cycles of latency, and you should make this choice early in the design definition, based on the bandwidth and host-controller capabilities. At speeds greater than 250 MHz, the CQ and CQ# echo clocks clock the data from the SRAMs; hence, QDRII+ requires no C and C# clocks, and the memory controller should use echo clocks CQ and CQ# to latch the read data from the SRAM when using QDRII+. For easier board design, QDRII+ adds a QVLD pin, which aligns with the edge of the echo clocks and occurs a half-cycle before the valid data. Hence, you should modify the board to include the QVLD signal and to take advantage of it when designing for QDRII+. QDRII devices use the P6 and R6 balls as a NC (no-connect) ball, requiring that designs using QDRII+ devices not to use output clocks C and C#. Also, Ball P6 should be pulled high with a 1-kΩ resistor. This approach helps in disconnecting the resistor to float the ball when designing with QDRII+. In DDRII+ (double-data-rate II+), because it does not support linear-burst addressing, balls A0 and A1 are nonconnects. QDRII+ has a 2048-cycle DLL-lock, whereas QDRII has a 1024-cycle time. QDRII+ also modifies the tKHK#H (K-clock-rising-edge-to-K#-clock-rising-edge) parameter to 42.5% from 45% of the input-clock cycle.

QDRII+ devices let designers achieve high performance and bandwidth for their designs with few changes to boards and to create new designs. By designing boards and host controllers to meet both QDRII and QDRII+ requirements, systems can support speeds as high as 500 MHz or bandwidth as high as 72 Gbps without changing boards or host controllers.


Author Information
Jayasree Nayar has a master’s degree in electrical engineering from Santa Clara University and is a staff applications engineer in the Memory and Imaging Division of Cypress Semiconductor. You can reach her at njy@cypress.com.


QDRII- and QDRII+-interface signals

Table A lists the clock, control, address, and data signals for pins on QDRII (quad-data-rate II)- and QDRII+-SRAM devices. A detailed description of these interface signals follows.

QDRII and QDRII+-SRAM devices have K and K# input clocks, C and C# output clocks (QDRII only), and CQ and CQ# echo clocks. The positive input clock, K, is the logical complement of the negative input clock, K#. Similarly, C and CQ are complements of C# and CQ#, respectively. The QDRII- and QDRII+-SRAM devices use the K and K# clocks for write accesses and the C and C# clocks for read accesses. CQ and CQ# are the source-synchronous output clocks from the QDRII- or the QDRII+-SRAM device that accompanies the read data. The number of loads that the K and K# clocks drive affects the switching times of these outputs. When a controller drives a single QDRII- or QDRII+-SRAM device, C and C# are unnecessary because the propagation delays from the controller to the QDRII- or QDRII+ SRAM device and back are the same. To reduce the number of loads on the clock traces, QDRII- and QDRII+-SRAM devices also have a single-clock mode, which uses the K and K# clocks for both reads and writes. QDRII- and QDRII+-SRAM devices still use CQ and CQ# for the echo clock from the memory device to the memory controller. In this mode, the C and C# clocks tie to the supply voltage.

The memory-controller device provides the K and K# clocks and the data, address, and command lines to the QDRII- or QDRII+-SRAM device. For the controller to operate properly, the write data (D), address (A), and control-signal-trace lengths and propagation times should be equal to the K and K# clock-trace lengths. QDRII and QDRII+ SRAMs generate echo clocks CQ and CQ#, which are edge-aligned with the read data. The memory-controller device usually phase-shifts the CQ and CQ# signals and uses them to capture the read data. The CQ and CQ# signal-board trace length between the QDRII or QDRII+ SRAM and the controller should be equal to the read-data (Q) board-trace length to minimize the skew between these signals.

QDRII and QDRII+ SRAM devices use two unidirectional data buses, D and Q, for writes and reads, respectively. QDRII+ SRAMs also have a QVLD (output-valid-indicator) pin. The QVLD signal aligns with the echo-clock edge and is high for approximately half a clock cycle before data is output from the memory. QDRII and QDRII+ SRAMs use the WPSn (write-port-select) signal to control write operations and the RPSn (read-port-select) signal to control read operations. The BWSn (byte-write-select) signal tells the QDRII or QDRII+ SRAM which byte to write into the QDRII or QDRII+ SRAM device. QDRII and QDRII+ SRAMs use one address bus (A) for both read and write addresses.

Click here for the table:

Table A