Cadence Design Systems has introduced Cadence C-to-Silicon Compiler, a high-level synthesis product that is said to improve designer productivity up to 10 times in creating and re-using system-on-chip IP. This technology helps bridge the gap between register transfer level (RTL) models—commonly used to verify, implement, and integrate SoCs—and system-level models, usually written in C/C++ and SystemC. The Compiler enables engineers to design at a higher level of abstraction and helps automate the analysis of hardware micro-architecture. Designer productivity is improved because the technology automatically translates and optimizes abstract behavioral descriptions from C/C++ and SystemC to synthesizeable Verilog RTL (including assertions) for implementation, verification and SoC integration.
