Overcoming the ASICs Challenge

By Stephen Las Marias, Editor


eAsic Corp. has launched its next generation Nextreme-2 Family, which is claimed to be the semiconductor industry's first 45nm, zero mask-charge ASICs. Manufactured on Chartered Semiconductor's 45nm low-power (LP) process and featuring an efficient LUT-based architecture, Nextreme-2 tout a 2.4TeraMACs of DSP capability without the need for embedded multipliers. Utilizing eASIC's patented power-management architecture, the Nextreme-2 family lowers power consumption by 80 percent when compared to state-of-the-art FPGAs, making it suitable for applications that demand power efficiency to help reduce system cost and meet stringent power budgets.

In an interview, CY Aw-Yong, Director Sales and Business Development, Asia Pacific, eASIC Corp. discusses the key features of the company's new ASIC family, as well as the challenges and opportunities in the ASIC industry. Excerpt:


How is the Nextreme-2 family different from the other solutions in the market?
This announcement is tapping upon our success in our Nextreme 90nm product. Nextreme-2 now provides better performance up to 700Mhz core, up to 20Mil gates, 30Mil bits DP memory, and 56x6.5Gbps MGIO for high speed communications. This will create a new standard for ASIC suppliers and FPGA vendors to match speed, power, cost and time-to-market for a secured customized IC.

What will be the dominant end application segments for the new Nextreme-2 family, and what functionalities does this provide on these specific segments?
All logic computations can now be realized using Nextreme2 family, such as thin client computing, video codec, network controls, medical imaging, industrial controls, printers and projector, GPS, etc. Where-else Nextreme2-T is more targeted at high performance applications such as switches, routers, traffic management, metro-transmission, mobile backhaul, WiMAX/femto repeaters, etc.

What can you say are the important performance characteristics of Nextreme-2 that will benefit the said segments?
Mainly the availability of high-speed logic and memory resources, stable EDA and architecture, high-speed MGIOs, and its being an economical and quick solution.

Do customer requirements/feedbacks affect your designing these types of products? How do you address them?
Yes, and we have taken their feedback and architecture improvement realized on the Nextreme-2 product, such as more eCells for compute intensive networking design.

What design strategies did you employ to enhance what we can say as the ¡°key features¡± of the Nextreme-2?
To keep the Nexteme-2 family as economical as possible, using single VIA layer to complete our customers' design. We have also taken special care to reduce power, for usage in mobile applications.

What were the challenges that eASIC designers faced as you moved into the 45nm process node?
It has to work first time. And our engineers deliver to their commitment; putting eASIC on the top 10 companies who are offering solutions on the 45nm node at this time.

Overall, what can you say will be the impact of the release of Nextreme-2 ASICs in the semiconductor industry?
Quoting my CEO, Ronnie Vasishta, 'We are already driving a reversal in the trends of declining ASIC design starts.' eASIC aims to proliferate the ASIC innovations by providing performance chip at zero mask-fees, and quick time to market at customer's volume of production.

What were the major technological changes that have come over the ASIC industry and how did eASIC face these challenges?
The semiconductor industry has been pushing the technology envelop, ever challenging Moore's law toward finer geometry. eASIC has adopted the proven Chartered 45nm LP process to design our Nextreme-2 product, and we worked very closely with our supply chain—foundry, EDA vendors, IP partners, assembly and test—to make this solution possible for our customers.

How do you see the market competition between ASICs and FPGAs? Do you expect FPGAs to eventually eat into the market of ASICs?
FPGA claims to replace ASIC based on certain assumptions: that ASIC is risky due to high mask cost, long design time and possibility of re-spin due to error. They compete on flexibility and quick logically simulation on board. However, FPGA is still not able to offer lower power, higher performance with embedded processor, and security of custom ASIC. This is reflected in the closed to ten-fold difference in market TAM.

The eASIC solution has nulled the FPGA assumptions on ASIC implementation, while providing the same performance, power and security at a fraction of the cost.

Some applications earlier are using ASICs but are now using FPGAs. How do you see this affecting the ASIC industry?
As explained above, mask cost for 90nm is now $500K; 65nm, $750K; not to mention EDA investments and shrinking market window to a full ASIC spin, which takes up to nine months. Only customers who have the money and market leadership can afford standard cell ASIC. However, any FPGA customers can now move to eASIC.

What are the key challenges facing the ASIC industry in the several months and what strategies are being put up in place by eASIC to address those?
Cost and risk management has been, and will continue to plague the ASIC market. We are offering zero mask cost solution, at no minimum order quantity, and quick turn-around to capture the market opportunity window.

How important is Asia in eASIC¡¯s business plans? Please tell us some of the upcoming developments from eASIC, as well as its planned business and manufacturing activities in Asia this year.
Asia is one of our critical supply chain bases, with foundry and test and assembly all done here. eASIC has engineers in the regional offices to provide local support to our customers. We are growing rapidly in terms of design wins, and it just show how our Asian companies have evolved to adopt new disruptive technology to win in the global market.

We are organizing private technical seminars within the next six months, and also participating in two tradeshows on September 2008.

Click here for more information on eASIC