Actel Offers Additional Power Reduction and Simplifies Design Creation with Libero IDE 8.4

Actel Corporation has announced new power reduction and design creation enhancements to its Libero Integrated Development Environment (IDE). Giving designers additional power supply options and enabling even lower power consumption, the new Libero IDE 8.4 offers an FPGA core operating voltage range from 1.14 to 1.575 volts for its flash-based IGLOO, IGLOO PLUS and ProASIC3L field-programmable gate arrays (FPGAs). Enhancements to the SmartPower analysis tools within the Libero IDE also allow easy comparisons of multiple design scenarios and their resulting power consumption and battery life implications. For rapid and efficient design creation, the Libero IDE 8.4 also allows Actel-created or third-party intellectual property (IP) blocks, user-developed HDL modules, and glue logic functions to be easily combined in an accessible project area.

New Enhancements to Libero IDE 8.4
The new Libero IDE 8.4 extends the FPGA core operating voltage range from 1.14 to 1.575 volts for its flash-based 1.2V IGLOO, IGLOO PLUS and ProASIC3L FPGAs, giving designers additional power supply options and enabling even lower power consumption. The Libero IDE 8.4 also includes enhanced SmartPower analysis capabilities. In the new tool suite, users can create and compare multiple user-defined power profile “scenarios”, enabling the user to test operating options to better determine the best design approach for their power-sensitive application. Offering users improved ease of use as well as a comprehensive understanding of power usage in all functional modes of the design, SmartPower also offers new graphical power consumption displays.

Conventional design methodologies include ground-up generation of HDL code or schematic designs to create and stitch the necessary combination of logic functions that make up the FPGA system or sub-system. The improvements to SmartDesign within Libero IDE 8.4 allows users to import user- or third-party created HDL modules, IP, and glue-logic functions into the project area. The user is then able to quickly select the desired blocks from among the imported functions or the existing catalog of IP cores and drop them onto an enhanced white board-like ‘canvas’ where they are viewed and connected in a system block diagram. In the end, a design rule checked and synthesis-ready HDL file is created. SmartDesign supports the quick building of simple designs or sophisticated complex processor-based system-on-chip solutions.

Actel