New Video Timing Reference Design Enhances Jitter Performance of Xilinx Virtex-5 LXT Platform
(Product News, 29 Sep 2008 )
National Semiconductor has introduced a new video clock reference design, now available as a module for the Xilinx ML571 serial digital video development board. National’s module improves the jitter performance of the ML571 board’s SERDES-optimized Virtex-5 LXT field-programmable gate arrays (FPGAs) and enables popular FPGA-based video solutions to easily meet the stringent Society of Motion Picture and Television Engineers (SMPTE) 424M jitter specifications. The reference design module simplifies the development of video cameras, digital recorders and a wide range of video editing and post-production equipment.
National’s ML571-1982CLK reference design clock module plugs into the Xilinx ML571 development board to create a complete video reference design for triple-rate (3G/HD/SD) SDI applications. The ML571-1982CLK delivers the industry’s lowest clock output jitter of 40 ps peak-to-peak (at 148.5 MHz) to drive the Virtex-5 LXT FPGA’s integrated SerDes without the need for additional clock cleaning circuitry.
The reference design module features National’s highly integrated LMH1982 multi-rate video clock generator and LMH1981 sync separator devices. The LMH1982 produces a top of frame (TOF) timing pulse output and can generate two simultaneous standard-definition (SD) and high-definition (HD) output clocks genlocked to the recovered H and V syncs from either a Xilinx Virtex-5 LXT FPGA, or from the outputs of a LMH1981 sync separator.
The LMH1982 supports NTSC/525i, PAL/625i, 525p, 625p, 720p, 1080i and 1080p video timing. This 5 mm by 5 mm device requires only one external 27 MHz voltage-controlled crystal oscillator (VCXO), which significantly reduces board space and design complexity. In the event of a loss of reference, the LMH1982 can be configured to default to either free run or holdover operation. In addition, the LMH1982 features a programmable charge pump current-control register for dynamic control of phase-lock loop (PLL) bandwidth. This allows a wide-loop bandwidth to be programmed for faster PLL lock time or a narrow-loop bandwidth for maximum input attenuation.
