Developing SATA/SAS Solutions Using 40nm FPGAs

Serial ATA (SATA) and Serial Attached SCSI (SAS) are computer bus standards that have the primary function of transferring data (directly or otherwise) between a motherboard and mass storage devices (such as hard disk drives, optical drives, and solid-state disks) inside and outside the computer. These serial storage protocols offer several advantages over older parallel storage protocols (ATA and SCSI) interfaces:
- More reliable operation
- Faster data transfer
- Ability to remove or add devices while operating (hot swapping) (only when supported by the operating system)
- Thinner cables for more efficient air cooling

Cables and connectors for SATA and SAS are interchangeable to a certain extent, in that a SATA storage device, cable, and connector can be used by a SAS host controller, but a SAS storage device and connectors cannot be used by a SATA host controller. This flexibility enables system designers to design for SAS, a higher performance and higher cost solution, but use SATA as a lower cost option. Several versions of the SATA and SAS standards have been released; with each version primarily addressing the speed of a single data link (see Table 1).

APPLICATIONS USING SATA AND SAS
Because SATA and SAS are storage protocols, they are used as an interface to storage devices. These storage devices that use the SATA and SAS protocols reside in appliances like PCs, JBODs, disk arrays (SAN and NAS), multifunction printers, set-top boxes, and any other appliance that requires data to be stored for any length of time. Figure 1 depicts a typical appliance in which SATA or SAS would be used.

SATA is used in cost-sensitive applications, like PCs, set-top boxes, SOHO storage enclosures, and other consumer-based applications. Designed as a replacement for ATA/IDE, this protocol predominantly is found in devices where low cost is essential.

In comparison, SAS is used in higher end systems, like SAN and NAS disk arrays, that are designed for high availability and little to no down time. These systems typically reside in data centers and provide five (5) nine’s (9’s) of availability, which means up-time 99.999% of the time. Applications needing this type of fault-tolerant storage are in the banking and stock trading industries. This type of reliability offered by SAS comes with a higher price tag, a justifiable return on investment when handling mission-critical data storage. SAS was designed as a replacement for SCSI, the protocol previously used for this type of storage.

FPGA USE OF SATA AND SAS
Supporting a storage interface is just one of many different application needs to which an FPGA can conform. However, providing SATA and SAS storage interfaces is just one way an FPGA can be used in storage appliances. The FPGA also can bridge different protocols, such as bridging simple bus I/Os like PCI Express (PCIe) to SATA or SAS, or more exotically, bridging network interfaces such as Gigabit Ethernet (GbE), Fibre Channel, or SONET to SATA or SAS. In addition, an FPGA provides value-added functions to simple bridging applications, making the FPGA a system on chip (SOC). These value-added SOC functions include RAID, data compression, packet processing, and more. By enabling development of SOC solutions, the FPGA simplifies system design, meaning that the FPGA reduces the need for multiple discrete devices by consolidating those functions in a single device. Figure 2 demonstrates how an FPGA integrates functions to create an SOC for a RAID controller.

An FPGA offers an excellent platform to integrate many discrete ASIC or ASSP functions into a single chip solution. With FPGAs from Altera supporting SAS and SATA natively with integrated transceivers, it enables the integration option for storage applications.

SATA/SAS SOLUTIONS
SATA and SAS solutions have been developed by Altera based on the 40nm Stratix IV GX and Arria II GX FPGAs with transceivers and HardCopy IV GX ASICs with transceivers. These FPGAs and ASICs, coupled with SATA and SAS intellectual property (IP), offer a solution for developing storage interfaces on a single chip. This section describes which SATA and SAS standards are supported by Altera transceiver solutions, the electrical specification compliance of the transceivers (Figure 2), and the IP used for SATA and SAS.

THE HARDWARE SOLUTION
The transceivers comply with the electrical standards for both SATA and SAS. Compliance to these electrical standards is accomplished using either built-in features in the transceiver block or with a small number of logic-based designs. Altera’s partner companies have several IP offerings that complete the SATA and SAS solutions, ranging from SATA 1 to SAS 2 in both host and device modes, which are summarized in Table 2.

SATA/SAS IP SOLUTION
The IP portion of this solution is core to the SATA and SAS I/O connectivity. The FPGA and ASIC provide the foundation, but the IP makes the SATA and SAS I/O possible. There are SATA and SAS IP for both host and device interfaces that have been developed by partner companies. Figure 3 shows the IP core with all the basic components of a SATA and SAS interface: a physical layer interface that connects to the embedded transceivers, a link layer, and a transport layer. In addition, the IP core includes a processor interface that provides a pathway for a host system to monitor core and provide control instructions. The core uses the 8b/10b coding block, the DPRIO block, and the signal detect and electrical idle, all in the transceivers for protocol coding, speed negotiation, and out-of-band signaling.

BUILDING A SATA AND SAS SOLUTION WITH IP AND FPGAS
To demonstrate the capability of this FPGA-based SATA and SAS solution is with a design that can test both host and target (device side) functions. This can be done in an FPGA by using a host or device IP core, a FPGA, and a host controller in a PC or disk drive. While SATA is used in Figure 4, either a SATA or SAS core may be used in the host or device designs. In the target design, the FPGA acts as a storage device for the host controller in the PC. In the host design, the FPGA performs host controller functions and stores data on the hard drive. The SATA host controller reads and writes data to and from the SATA hard disk drive, and a SATA target provides an endpoint storage interface for stored data to the PC.

The FPGA and IP provide the foundation for SATA interface to both host and target devices, but more is needed. For a complete target (device) solution, a storage device like a hard drive or flash drive must be connected to the FPGA. A complete host solution needs application layer software added to the IP to enable data to be passed from one application to a storage device connected to the FPGA. Both the host design and target design are used for interoperability and industry compliance testing, as these allow both host and device functionality to be verified.

ALTERA DEVELOPMENT PLATFORMS
For design validation testing, Altera uses the Stratix IV FPGA and a SATA/SAS I/O connector. The platform includes the Stratix IV GX signal integrity board used in conjunction with an SMA to SATA paddle card for SATA I/O connectivity. This creates a hardware development platform for SATA/SAS testing. The hardware platform plus a soft SATA/SAS IP core can be used for functionality, specification-compliance, interoperability, and performance testing.

CONCLUSION
Altera’s 40nm FPGAs and ASICs with transceivers provide an excellent way to develop SOC solutions for storage applications. The FPGA fabric enables system designers to integrate more functions in a single-chip solution, simplifying solution design and enabling integration of transceivers for SATA/SAS I/O connectivity. Altera’s portfolio of 40-nm FPGAs and ASICs transceivers in combination with SATA/SAS IP cores creates an interface that can be used for a SATA/SAS solution.

Caption
Table 1. SATA/SAS Standards and Speeds
Table 2. Altera Hardware Compliance

Figure 1: SAS Disk Array Example
Figure 2: A Typical SOC Example
Figure 3: SATA/SAS IP Core
Figure 4: Host (left) and Device (right) Design Examples

Click here for the illustrations:

Figure 1, Figure 2, Figure 3, Figure 4, Table 1, Table 2