DAC and flip-flops form constant-current source

The Analog Devices AD5422 16-bit serial-input DAC lets you program for a voltage output or a current output. To communicate with the DAC and produce a variable output, you need a data SERDES (serializer/deserializer). If your design needs a constant 4-mA output, however, you can program the device with two flip-flops and test it with S₁, a mechanical pushbutton switch (Figure 1).

The AD5422’s programming uses a 24-bit word in which the upper eight bits form an address for a control register and the lower 16 bits set the DAC’s output range, slew-rate step, and slew-rate clock (Table 1). Programming a 24-bit 0101 ... 01 pattern into the AD5422 sets it to the bottom of the simultaneously selected current range, 4 to 20 mA at the output-current pin (Pin 19). The AD5422’s internal shift-register data moves into the data register at every low-to-high transition of the latch signal (Pin 7). The device interprets this alternating bit sequence as a control command during the 23rd time you press and release the switch after IC₁’s power-up. After that sequence, the SCLK signal can remain idle (Figure 2).

Flip-flop FF₁, configured as a familiar divide-by-two counter, produces the desired alternating sequence. Manually pressing and releasing the pushbutton switch, you cause the generation of an SCLK signal. You must use a debouncer because the circuit requires a clean logic signal for SCLK with level transitions that do not exceed a few 10s of nanoseconds. FF₂ acts as an asynchronous set/reset flip-flop that debounces the signal from the button.

For the circuit to work properly, the active low-to-high transition of the latch signal must occur at least 13 nsec after the low-to-high transition of SCLK. You can fulfill this requirement by using the SN74HC74-class flip-flop. The Q output of FF₁ in IC₂ connects to the SDIN input of IC₁. The level transitions at the SDIN input must have preset and hold times of at least 5 nsec with respect to low-to-high transitions of the SCLK signal. You can derive the supply voltage of 5V for the pull-up resistor at the output of IC1 (Pin 3) for IC₂ from the AD5422’s precision 5V reference. The tiny current surges due to loads appear at the initializing state, at clocking in the control word to IC₁, or in a faulty state when the open-drain output of IC₁ is active. Fortunately, either the output current (Pin 19) is not yet flowing, or an overtemperature condition or an excessive value of the load resistor causes external damage to the precision of this current. In either case, the external loading of the internal reference source, which is no more than a few 10s of microamperes, is harmless to the precision of the reference source.

By connecting a high-precision, 100Ω resistor between the IOUT pin and ground and generating 23 clock pulses, you can measure a voltage of 0.400xV on this resistor, where x≤4, confirming the high-precision, constantly flowing current of 4 mA. The actual full-scale-range error of IC₁ is far below its guaranteed worst-case value of ±0.3% full-scale-range error (Reference 1). Hence, you must divide the observed relative error of the 4-mA current, with a value not exceeding 0.1%, by four because the current scale is 20 mA–4 mA=16 mA. The total full-scale-range error of the DAC in this case is thus less than 0.1%/4, or 0. 025%. By using the constant-current source employing a monolithic DAC, you get high resolution, negligible sensitivity to temperature, immunity to supply-voltage variations, and high initial accuracy. Current-output DACs also exhibit output resistance in the 10s of megohms.

This circuit uses S₁ to generate the SCLK signal for testing purposes only. For power-on-the-go applications, you can use a free-running clock with a frequency as high as 200 kHz. You can supply the pull-up resistor at the output and IC₂ from the AD5422’s DVCC pin.


The AD5422’s programming uses a 24-bit word in which the upper eight bits form an address for a control register and the lower 16 bits set the DAC’s output range, slew-rate step, and slew-rate clock (Table 1). Programming a 24-bit 0101 ... 01 pattern into the AD5422 sets it to the bottom of the simultaneously selected current range, 4 to 20 mA at the output-current pin (Pin 19). The AD5422’s internal shift-register data moves into the data register at every low-to-high transition of the latch signal (Pin 7). The device interprets this alternating bit sequence as a control command during the 23rd time you press and release the switch after IC₁’s power-up. After that sequence, the SCLK signal can remain idle (Figure 2).

Flip-flop FF₁, configured as a familiar divide-by-two counter, produces the desired alternating sequence. Manually pressing and releasing the pushbutton switch, you cause the generation of an SCLK signal. You must use a debouncer because the circuit requires a clean logic signal for SCLK with level transitions that do not exceed a few 10s of nanoseconds. FF₂ acts as an asynchronous set/reset flip-flop that debounces the signal from the button.

For the circuit to work properly, the active low-to-high transition of the latch signal must occur at least 13 nsec after the low-to-high transition of SCLK. You can fulfill this requirement by using the SN74HC74-class flip-flop. The Q output of FF₁ in IC₂ connects to the SDIN input of IC₁. The level transitions at the SDIN input must have preset and hold times of at least 5 nsec with respect to low-to-high transitions of the SCLK signal. You can derive the supply voltage of 5V for the pull-up resistor at the output of IC1 (Pin 3) for IC₂ from the AD5422’s precision 5V reference. The tiny current surges due to loads appear at the initializing state, at clocking in the control word to IC₁, or in a faulty state when the open-drain output of IC₁ is active. Fortunately, either the output current (Pin 19) is not yet flowing, or an overtemperature condition or an excessive value of the load resistor causes external damage to the precision of this current. In either case, the external loading of the internal reference source, which is no more than a few 10s of microamperes, is harmless to the precision of the reference source.

By connecting a high-precision, 100Ω resistor between the IOUT pin and ground and generating 23 clock pulses, you can measure a voltage of 0.400xV on this resistor, where x≤4, confirming the high-precision, constantly flowing current of 4 mA. The actual full-scale-range error of IC₁ is far below its guaranteed worst-case value of ±0.3% full-scale-range error (Reference 1). Hence, you must divide the observed relative error of the 4-mA current, with a value not exceeding 0.1%, by four because the current scale is 20 mA–4 mA=16 mA. The total full-scale-range error of the DAC in this case is thus less than 0.1%/4, or 0. 025%. By using the constant-current source employing a monolithic DAC, you get high resolution, negligible sensitivity to temperature, immunity to supply-voltage variations, and high initial accuracy. Current-output DACs also exhibit output resistance in the 10s of megohms.

This circuit uses S₁ to generate the SCLK signal for testing purposes only. For power-on-the-go applications, you can use a free-running clock with a frequency as high as 200 kHz. You can supply the pull-up resistor at the output and IC₂ from the AD5422’s DVCC pin.

Click here for the illustrations:

Figure 1, Figure 2, Table 1

Reference
1. “Single Channel, 12/16-Bit, Serial Input, Current Source and Voltage Output DACs, AD5412/AD5422,” Analog Devices, 2008.

Caption
Figure 1: After you press and release S1 23 times, the DAC produces a constant-4-mA-current output.

Figure 2: Although the control-command sequence is at least 23 clock pulses wide, you can easily generate the alternating bit pattern.