PCB design software reduces the number of physical prototype iterations

Cadence Design Systems Inc.’s latest Allegro and OrCAD printed circuit board (PCB) software bring PCB engineers significant new benefits, including the ability to miniaturize the footprint of their end product and reduce the number of physical prototype iterations, making the design cycle more predictable. The Allegro and OrCAD PCB Design Release 16.3 addresses increased functional and interconnect density through improvements for rigid-flex routing, extended high-density interconnect (HDI) rules, 3D viewing of PCBs, and asymmetrical clearance for RF circuits.

The new release features extended micro via stacking rules, which allow users to create the most difficult HDI designs, and multi-line curved bus routing that hugs the flex outline, which accelerates the creation of rigid-flex designs. In addition, the new software has an integrated 3D PCB viewer, which gives designers visibility into components and HDI micro via breakouts, thus eliminating unnecessary iterations with mechanical design teams. The Allegro PCB RF Option also helps engineers speed the time to create accurate RF circuits through the use of asymmetrical clearances for one or more RF elements.

The latest Allegro and OrCAD release uses a multi-phase pre-release approach to help ensure that content and quality meet customers needs. Also featured are a number of significant productivity and usability improvements to the OrCAD family of products. For instance, OrCAD Capture CIS now offers autowire capability to quickly add connections, as well as new 3D footprint viewing. The OrCAD PCB Editor provides 3D viewing and “flip-board” design/editing and jumper support for single-sided PCB designs, while the OrCAD Signal Explorer has a revamped user interface, with drag-and-drop and copy-and-paste functionality, context-sensitive RMB functions and native IBIS model support.

Usability improvements are another focus of the latest Allegro PCB Signal and Power Integrity software, which offers a new user interface and adds stack-up-aware capabilities to the pre-route analysis environment. Buffer modeling standards are embraced through native IBIS and SPICE support, including Cadence Virtuoso Spectre Circuit Simulator models. Another improvement is the ability to quickly scan a PCB with dozens of multi-gigabit signals and quickly determine where detailed analysis should be applied as signals are ranked according to their signal-to-noise ratio.

Cadence Design Systems Inc.
www.cadence.com