Power efficiency is the way to go

At the Asiapress Tour 2009 held in California December last, one of the highlights was a panel discussion on one of the most important topics in the industry today: power. Moderated by Ron Wilson, Executive Editor of EDN magazine, the panel featured leading companies in their segments—Altera, Cadence Design Systems, Fairchild Semiconductor, and Intersil—discussing technology issues and developments when it comes to power consumption, and how the industry should address this problem that has become totally critical not just for high-performance systems, but actually in our daily lives.

Power consumption and margins and budgets are no longer a matter of just chip design anymore; it encompasses the hardware architecture, software choices, and even mechanical design decisions. That is why the panel discussion involved representatives from different segments of the industry—analog, FPGA, and electronic design automation (EDA). Although of course, there had been no definite consensus as to how the industry should move forward as one when it comes to this power consumption and efficiency issue, each company at least has given its own perspectives and solutions addressing this never-ending power question.

For one, Van Niemela, Fairchild Semiconductor’s Worldwide Technical Marketing Manager for Off-Line Power Supplies, said that the company has been employing its Deep Trench Technology to manufacture 600V Super-Junction MOSFETs targeted at power supplies, lighting, display and industrial applications. These devices feature very low RDS(ON) and total gate charge, bringing a 40 percent lower FOM and delivering 20 percent less switching and conduction losses, thereby resulting in higher efficiency.

Altera’s Dave Greenfield, Sr. Director, HardCopy ASICs, said that when it comes to silicon, designers should leverage advanced process technologies to lower the core voltages to bring down dynamic power. In software, he noted that the accuracy in estimation is a critical starting point, and that a key new option is on power-driven synthesis as opposed to the past priority on performance and density.

Steve Carlson, VP of Cadence, noted that there are many choices that are influential factors in architectural renaissance, including process nodes, lithography alternative, and packaging options, to name a few. He said that that one of the new methods now should be the early and accurate chip estimation, and that abstraction, this time, is for real.

Finally, Intersil’s Peter Oaklander, Sr. VP for Power Management Products, mentioned that efficiency must be looked at all points in the power chain, from generation to the AC-to-DC conversion and DC-to-DC at the load.

The industry, I believe, cannot solve the whole power problem by overhauling everything at once because there are a lot of other factors to consider. They have to start small, and little by little. And what more than to focus on the hearts of these systems—the semiconductors—as well as the power rails; putting power consumption efficiencies in these devices will eventually lead to big strides in power savings efforts across the value chain.