Power-aware Verification Spans IC Design Cycle

The mandate to reduce system power consumption and design energy-efficient ICs has led to the increasing use of low-power IC design techniques. In addition to well-established techniques like clock gating, IC designers today are using advanced techniques such as power shutoff, back body biasing, and dynamic voltage and frequency scaling (DVFS). More and more chips have multiple operating modes as well as multiple power domains with different, and perhaps dynamically variable, voltage levels.

The central problem with low-power verification is the explosion in scope and complexity caused by low-power design techniques. Some chips today have 20 to 50 power domains and hundreds of power modes. As a result, chips may have thousands or tens of thousands of possible power states. Verification engineers must ensure that the chip functions correctly in each state that could plausibly occur, and that all transitions between states are properly handled.

Because of this complexity, verification planning is essential for low-power designs. An ad-hoc approach is not likely to succeed. The verification effort should start with a measurable, executable plan that sets forth goals and priorities. This plan should guide verification efforts all the way to verification closure, which occurs when goals are met. Along the way, low-power design effects must be continuously analyzed and verified from the systems level to GDSII.

Different power optimization techniques have differing impacts on verification. For example, clock gating has a minor impact, multiple power domains and multi-Vt libraries have a moderate impact, and power shutoff, DVFS, and multiple operating modes have a major impact


Figure 1: Some advanced low-power design techniques have a profound impact on verification.

A “plan to closure” approach can ease power-aware IC verification tasks. Such an approach starts with a verification plan that is tracked through coverage metrics. It makes use of the Common Power Format (CPF) to capture power intent throughout the verification flow. This article discusses the use of behavioral simulation, RTL simulation, assertions, emulation, and formal verification for low-power verification. It looks at tough simulation challenges posed by techniques such as power shutoff and DVFS, and proposes some solutions.

REQUIREMENTS FOR LOW-POWER VERIFICATION
A successful low-power verification methodology requires these prerequisites:
• An executable, metric-driven verification plan. Verification planning brings all stakeholders together to capture the verification intent, and to identify criteria for verification closure. Because low-power design introduces a great deal of complexity into the verification environment, a measurable low-power verification strategy must be developed up front.
• A common view of the power architecture. There are a large number of tools in the low-power verification flow, and all must share a coherent view of the power architecture. In the Cadence Design Systems flow, the Common Power Format (CPF) provides that view.
• Tools with a native understanding of power intent. Simulators and other tools in the low-power verification flow need to understand low-power states and requirements. If a test unexpectedly forces a power event, for instance, the tool must be able to recognize that. This is only practical if a tool provides high performance for low-power verification.
• Reuse of existing IP and methodologies. A low-power verification approach must support a high degree of reuse, even if existing design and verification IP was not developed specifically for low power. The “side file” approach used by CPF, which does not require modifications to RTL code, is one step in this direction.
• Automated, early formal checking. Static checking can expose problems and verify changes in the power architecture with minimal impact to the rest of the verification environment.

POWER-AWARE VERIFICATION PLANNING
Defining an Architecture
The low-power verification flow begins when power architecture is defined for the design. This architecture partitions the design into major blocks and determines which power-saving techniques can be used by each block. As decisions are made about the power architecture, they need to be captured in a format that can be used by all tools. The Cadence flow uses CPF for this purpose.

An architect will create a system-level CPF file to define the top-level power domains and system-level power modes in the design. This file will typically include information that identifies the following:
• Major power domains
• Use of power shutoff, retention, isolation, level shifting, DVFS, multiple supply voltages, and other techniques
• Major modes of operation
• Power-up restoration policies
• Interface requirements between domains

The following code example shows how CPF describes power domains:


Figure 2: CPF code used to define a power domain.


AN EXECUTABLE PLAN
As the power architecture is defined, a corresponding verification plan must be developed. This plan allows all stakeholders to agree on what needs to be verified and how it will be verified. The plan defines verification closure and describes how to measure it. The planning process results in a machine-executable verification plan that can track the progress of the verifi¬cation effort using metrics such as functional coverage.

Verification planning is always important, but it is especially important for low-power design because the power architecture adds so much complexity to the verification. The verification space increases with each power mode, and the device must be validated in all modes.

Ideally each verification mode is fully validated, but often the verification space is too large for exhaustive verification. The verification planning process provides a documented analysis of the important modes and required verification. Verification engineers must understand which features are valid in each mode. Power modes must be entered and exited without errors, and transitions between power domains must be handled properly.

To fulfill these requirements, the verification plan should include a section on the verification of power intent. This section should describe the power modes and the requirements for exercising them. It should define the set of features that need to be verified in each of the design’s power modes. It should also define the features that are not available in given power modes. Figure 3 shows some of the power-related criteria that should be covered in a verification plan


Figure 3: A verification plan needs to include information about a variety of low-power design features.


In summary, the key items defined in the verification plan are:
• Description of power behavior
• Coverage items to ensure power behavior was tested
• Assertions and/or test scenarios to ensure the design operates properly

TOUGH CHALLENGE #1 – VERIFYING POWER SHUTOFF
Understanding how to deal with power shutoff (PSO) is one of the most critical aspects of power-aware verification. PSO has a significant impact on simulation, assertions, coverage, verification IP, and modeling. The first point to understand is what not to do. If PSO is defined in the CPF file, the user-defined verification environment should not attempt to model power shutoff corruption, state retention, or isolation inside the DUV. Doing so actually increases the chances of failure. The only exception to this statement is that some behavioral models, like RAM models, may require a signal that defines when power is shut off to the module containing the RAM.

TOUGH CHALLENGE #2 – VERIFYING DVFS
Static multiple supply voltage (MSV) designs have very little impact on the simulation environment. They can be completely verified with static checks to ensure that the voltage difference between two domains is within a given threshold, and if not, that level shifters are provided. This threshold is technology dependent but is generally less than 100mV.

If the static checks are clean, the different voltage levels will not change the logic values seen in simulation, and these voltage levels place no requirements on the simulation engine.

Dynamic voltage, however, does impact the simulation. First, simulation needs to verify power domains at all legal combinations of voltages. Secondly, the interfaces between power domains need to be checked to verify that a correct voltage is provided across the interfaces. If any problems arise, either isolation or level shifting should be used to protect the interfaces.

CONCLUSION
Functional verification is a difficult task – and low-power design makes it even more difficult. With today’s low power design techniques, ICs may have dozens or hundreds of different power modes and domains. The IC must function correctly in every possible power state, and transitions between power states must be correct. Power shutoff (PSO) and dynamic voltage and frequency scaling (DVFS) are particularly problematic from a verification standpoint.

A plan-to-closure methodology, complemented by power-aware verification tools and a common way of expressing power intent, can go a long ways towards easing the low-power verification challenge. Such a methodology begins with a verification plan based on the low-power archi¬tecture. The plan defines verification closure and describes how to measure it through coverage metrics.

ACKNOWLEDGMENT
This article is a re-purposed version of the white paper authored by John Decker, Neyaz Khan, and Richard Goering of Cadence Design Systems.

AUTHOR INFORMATION
Rahul Arya is the Marketing & Technical Sales Director of Cadence Design Systems (I) Pvt Ltd.