Low-power all-digital PLL designed for portable wireless terminals

NEC Corp. (NEC) and NEC Electronics Corp. (NECEL) have developed a low-power low-noise All-Digital Phase Lock Loop (ADPLL) LSI that is targeted at battery-powered portable wireless equipment. The 0.37mm2 LSI features low-operation current of 8.1mA and lock-up time of only 20μs. Its low-phase noise of -105dBc/Hz in the frequency range of 2.1GHz to 2.8GHz makes it compatible with a wide variety of modern wireless systems, including Bluetooth, ZigBee, Wi-Fi, and WiMAX.

NEC’s ADPLL LSI’s TDC (Time-to-Digital Converter) has a new architecture that can achieve high accuracy in time-domain signal processing with reduced power consumption. The architecture is based on a fine/coarse two-step phase comparison scheme that can greatly reduce the number of circuit elements to be powered in each timing-comparison step. Using such architecture, only a fraction of the PLL circuit is powered, minimum time is required and the other circuits are automatically shut down. NEC has also employed another design to achieve a low phase noise, wherein a random signal has been intentionally added to the oscillator to suppress undesired noise originating from digitally periodic control.

NEC Corp.

NEC Electronics Corp.