Mentor adds SystemC support to Catapult C

Mentor Graphics has continued to expand the reach of its product with its core Catapult C synthesis engine. In December, the company added support for control-logic synthesis and some level of power management. The company has now taken another step, adding a preprocessor that makes SystemC code into a form that the Catapult C engine can use.

For some people, SystemC is a way to document and explore systems at the transaction level. For some, it is a cycle-accurate tool for creating test benches. For still others, it’s the first stage in synthesizing an actual design. Each of these users employs a different subset of the language and uses code in a different way. In an attempt to please almost all of these users, the tool handles abstract, untimed C++ code, TLM (transaction-level-modeling) 2.0-compliant SystemC, and cycle-accurate SystemC, employing, for example, the wait construct, according to Shawn McCloud, product-line director at the company.

Mentor is emphasizing the accurate representation and synthesis of complex bus interfaces and, in some instances, on-chip interconnect. The ability to generate production-quality RTL (register-transfer-level) logic from SystemC representations of these structures combines with Catapult C’s ability to generate useful RTL logic for functional blocks to bring the tool closer to the goal of digital full-chip synthesis.

Accordingly, Mentor provides SystemC creation and simulation in Vista, including lint, coverage, and runtime-checking tools. After synthesis, Catapult generates insertions into your RTL to assist in Questa RTL debugging. You can also synthesize much of your SystemC test bench and reuse it at RTL.

HLL (high-level-language)-synthesis tools are increasingly addressing the full range of needs of a design team at both the block and the full-chip levels. But even as HLL tools improve, the design community continues to increase its reliance on IP (intellectual-property) blocks and IP-integration methods. The long-term importance of these tools may lie in their ability to describe, model, and refine an assembly of IP rather than their ability to create a chip from a sheet of paper.

Mentor Graphics