Precisely measure settling time to 1ppm

Instrumentation, function generators, inertial navigation systems, ATE (automatic test equipment), medical apparatus, and other precision applications now require 18-bit converters. The resolutions of these converters are so precise that measuring various performance parameters is difficult. DACs’ dc specifications are relatively easy to verify, but their ac specifications require more sophisticated approaches to produce reliable information. A DAC’s settling time is the elapsed time from an input code application until the output remains within a specified error band around the final value. The settling time of a DAC and its output amplifier is difficult to determine at 18-bit, or 4-ppm, resolution. To measure an 18-bit DAC, you must use measurement techniques with 20-bit, or 1-ppm, resolution for settling times as short as 265ns. Manufacturers usually specify DACs’ settling times for a full-scale 10V transition.

Measuring anything at any speed to 20-bit, or 1ppm, resolution is difficult (see sidebar “Components for 18-bit digital-to-analog conversion”). Dynamic measurement to 20-bit resolution is particularly challenging. Reliable 1ppm DAC-settling-time measurement constitutes a difficult problem requiring exceptional care in approach and experimental technique. You can use an oscilloscope to accurately display DAC-settling-time information for a 10V step with 1ppm, or 10µV, resolution within 265ns. The approach permits observation of small amplitude information at the excursion limits of large waveforms without overdriving the oscilloscope.

DAC settling time has three distinct components: delay time, slew time, and ring time (Figure 1). The delay time is small and is almost entirely due to propagation delay through the DAC and the output amplifier. During this interval, no output movement occurs. During slew time, the output amplifier moves at its highest possible speed toward the final value. Ring time defines the region in which the amplifier recovers from slewing and ceases movement within some defined error band. A trade-off between slew and ring time normally exists. Fast-slewing amplifiers generally have extended ring times, complicating your amplifier choice and frequency compensation. Additionally, the architecture of fast amplifiers usually dictates trade-offs that degrade dc error terms (see sidebar “DAC-amplifier compensation”).


FIGURE 1

DAC settling time
Engineers have previously measured DAC settling time with the false-sum-node technique (Figure 2). The resistors and DAC form a bridge-type network. With ideal components, the DAC output steps to the negative reference voltage when the DAC inputs move to all ones. During slew, the diodes, which limit the voltage excursion, bind the settling node. When settling occurs, the oscilloscope probe’s voltage should be 0V. The resistor divider’s attenuation means that the probe’s output will be one-half of the DAC’s settled voltage.


FIGURE 2

In theory, this circuit allows you to observe settling to small amplitudes. In practice, you cannot rely on the circuit to produce useful measurements. The oscilloscope connection presents problems. As probe capacitance rises, ac loading of the resistor junction influences the settling waveforms. A 10pF probe alleviates this problem, but its 10× attenuation sacrifices gain. Probes with 1× attenuation are not suitable because of their excessive input capacitance. An active 1× FET (field-effect-transistor) probe works but still presents a more significant issue: oscilloscope overdrive.

The clamp diodes at the settling node reduce swing during the amplifier’s slewing, which prevents the circuit from overdriving the oscilloscope. Unfortunately, oscilloscope-overdrive-recovery characteristics vary widely, and manufacturers do not usually specify them. The 400mV drop across the Schottky diodes means that the oscilloscope may see an unacceptable overload.

An oscilloscope typically undergoes a 2× overdrive when you set it to 50mV/division while measuring to a 10-bit resolution. A 10-bit resolution—10mV at the DAC output—results in 5mV at the oscilloscope. The desired 5mV baseline is just discernible. At 12-bit or higher resolution, the measurement becomes hopeless. If you increase the oscilloscope’s gain, you also increase overdrive-induced errors. At 18 bits of resolution, there is no chance of measurement integrity.

Measuring 18-bit settling time requires a high-gain oscilloscope that is also immune to overdrive. You can address the gain issue by using an external wideband preamplifier that accurately amplifies the diode-clamped settling node. Only classic sampling oscilloscopes, which vendors no longer manufacture, offer inherent overdrive immunity. However, you can construct a circuit that uses sampling techniques to avoid the overload problem. You can also endow the circuit with features for measuring 20-bit DAC settling time.

To measure 20-bit DAC settling time, you connect the settling point to the preamplified oscilloscope with a switch (Figure 3). You control the switch state with a delayed pulse generator, which you trigger with the same pulse that controls the DAC. You arrange the delayed pulse generator’s timing so that the switch does not close until settling is nearly complete. In this way, you sample the incoming waveform in both time and amplitude. The oscilloscope never experiences overdrive, and no off-screen activity occurs.


FIGURE 3

The sampling switch has stringent requirements. It must faithfully pass signal-path information without introducing alien components, including those from the switch-command channel. Conventional choices for the sampling switch are JFETs (junction FETs), MOSFETs (metal-oxide-semiconductor FETs), and diode bridges (Figure 4).


FIGURE 4

The parasitic gate-to-channel capacitances of FETs result in a large feedthrough into the signal path from the gate drive. This feedthrough is many times larger than the signal you are observing, and it obviates the switch’s purpose. The small parasitic capacitance and the symmetrical differential structure of a diode bridge tend to cancel the drive signal and result in low feedthrough. You must perform dc and ac trims and use complex drive and support circuitry with a diode bridge. You can reliably measure DAC settling time to 16-bit resolution. Beyond 16 bits, residual feedthrough becomes objectionable, and you must use another approach.

You can construct a low-feedthrough, high-resolution switch using wideband active components. With this approach, you can maintain the switch’s control channel inband because its transition rate is within the circuit’s bandpass frequency. The circuit’s wide bandwidth means that you can always control the switch’s transition. You greatly reduce feedthrough by having no out-of-band response.

Some candidates for low-feedthrough electronic switches are theoretically possible but cumbersome to implement (Figure 5a and Figure 5b). You must optimize others for low feedthrough on the rising and falling control-pulse edges because of the multiplier’s unrestricted wideband response (Figure 5c). You can minimize falling-edge feedthrough by using the collapse of an amplifier’s transconductance when the control pulse goes low (Figure 5d). This approach allows you to minimize the feedthrough of the control pulse’s rising edge without regard to falling-edge effects. This feature provides a significant advantage for an electronic switch.


FIGURE 5

An electronic-circuit sampling switch uses a transconductance amplifier (Figure 6). The switch dynamics are exceptionally pure because the wideband control and signal paths faithfully track a 1000-to-1 transconductance change. You can carefully optimize the switched current source for the lowest feedthrough on the rising control edge without regard to the falling-edge characteristics. The transconductance collapses on the falling edge, which ensures low feedthrough for that condition. This technique prevents oscilloscope overdrive.


FIGURE 6

The detailed design switches signals over a ±30mV range with peak control-channel feedthrough of only millivolts and settling times of less than 40ns (Figure 7). The unity-gain circuit approximates switch action by varying A1A’s transconductance. The amplifier and its transconductance-control channel are wideband components, permitting them to faithfully track rapid variations in a transconductance setting. This characteristic means that the amplifier is always in control, affording clean response and rapid settling to the input’s value.


FIGURE 7

Amplifier A1A is the wideband transconductance amplifier. You set its voltage gain by the current magnitude into its ISET (current-set) terminal and its output-resistor load. Amplifier A1B unloads A1A’s output. This amplifier provides a gain of two. When driving a back-terminated 50Ω cable, however, its effective gain is unity at the cable’s receiving end. The back termination establishes a 50Ω signal-path environment. The switch-control input controls current source Q1, which sets A1A’s transconductance and gain.

Q1 is gated off when you set the switch-control input at zero. The 10MΩ resistor supplies 1.5µA into A1A’s ISET pin, which results in a voltage gain of nearly zero. This action blocks the input signal. When you set the switch-control input high, Q1 turns on, sourcing 1.5mA into the ISET pin, in turn forcing maximum transconductance and causing the amplifier to assume unity gain and pass the input signal. You use trims for zero and gain to ensure accurate input-signal replication at the circuit’s output. You purify turn-on switching with a 50pF variable capacitor and use a 10kΩ thermistor with a 3300-ppm/°C temperature coefficient at Q1. This approach compensates A1A’s transconductance temperature dependence to minimize gain drift.

When you set the aberration capacitance to 35pF, the circuit cleanly switches a 10mV input signal (Figure 8). When the control input (Trace A) is low, no output (Trace B) occurs. When the control input goes high, the output reproduces the input with feedthrough settling in 20ns. You don’t see turn-off feedthrough due to the transconductance reduction of 1000-to-1 and the attendant 25-fold decrease in the frequency bandwidth. You set the sweep speed to 10ns/division to examine the 0V-settling details (Figure 9). The output (Trace B) settles to within 1mV within 40ns after the switch control (Trace A) goes high. The aberration capacitance damps the peak feedthrough excursion of 5mV. If you set this capacitance to 0pF, feedthrough increases to 20mV (Figure 10). Settling time to within 1mV remains at 40ns. Setting this capacitance to 35pF minimizes the feedthrough amplitude but yields seven-times-higher rise time than is possible with a setting of 0pF (Figure 11).

FIGURE 8 HERE

FIGURE 9 HERE

FIGURE 10 HERE

FIGURE 11 HERE

The small dc and ac error of a transconductance switch accommodates the application’s requirements. The low feedthrough becomes irrelevant because the DAC’s ring-time interval buries the small time and amplitude error, pointing the way toward practical 1-ppm DAC-settling-time measurements.

Measurement method
You can combine this electronic switch with the DAC-amplifier summing method (Figure 12). You split the delayed pulse generator into independently variable delay and pulse-generator blocks. You run the input step to the oscilloscope through a section that compensates for settling-time-path propagation delays. This path includes the settling node, the amplifier, and sample-gate delays. You drive the transconductance sampling switch from a nonsaturating residue amplifier, feeding the oscilloscope. Placing the sampling switch after the residue amplifier further minimizes sample-command feedthrough.


FIGURE 12

The 20-bit DAC-settling-time-measurement circuitry uses the input pulse to simultaneously switch all the DAC bits (Figure 13). You must use a modified circuit and a Microchip PIC microcontroller for serial DACs (see sidebar “Settling-time measurement of serial DACs”). You also route this pulse to the oscilloscope through the delay-compensation network, which comprises CMOS inverters and an adjustable RC network. It compensates the oscilloscope’s input step signal for the 44ns delay through the circuit-measurement path (see sidebar “Delay and circuit-trimming procedures”). You compare the DAC-amplifier output with the 10V reference using precision 10kΩ summing resistors. The reference IC also furnishes the DAC reference, which makes the measurement ratiometric. A1, which also has voltage gain, unloads the clamped settling node. Amplifier A2 has a clamped output and provides a total amplification of 40 referred to the summing node. A2’s output feeds the sampling-switch circuit. The potentiometer adjusts the circuit’s gain.


FIGURE 13

You arrange the clamping and gain of A1 and A2 so that saturation never occurs. The amplifier is always in its active region. The input pulse triggers the 74HC123 dual one-shot. You control the pulse delay of the one-shot with a 20kΩ potentiometer. If you set the delay appropriately, the oscilloscope sees no input signal until settling is nearly complete, thereby eliminating overdrive. You adjust the sampling switch’s on-time so that you can observe all remaining settling activity.

When the sample gate goes high, switching is clean, and you can easily observe the last millivolt of ringing time (Figure 14). The amplifier settles nicely to a final value. When the sample gate goes low, the transconductance switch goes off, and you can discern no feedthrough. There is never any off-screen activity, and the oscilloscope is never in overdrive.


FIGURE 14

To achieve this level of performance, you must trim the circuit (see sidebar “Delay and circuit-trimming procedures”). If you do a poor sample-interval-zero adjustment, the circuit shifts the output baseline (Figure 15). A proper adjustment yields a continual baseline (Figure 16). You can see the barely visible sample-command feedthrough at Trace B’s leading edge. Signal peaking goes to 350µV, and settling is 50ns before your trimming aberrations and transition purity (Figure 17). By trimming these functions, you increase delay to 70ns from 20ns, but the signal peaks at only 50µV (Figure 18). Signal settling remains at 50ns. At the sample-command turn-off, the 1000-to-1 transconductance drop ensures a clean transition independent of the turn-on optimizing trims (Figure 19).


FIGURE 15 HERE

FIGURE 16 HERE

FIGURE 17

FIGURE 18 HERE

FIGURE 19 HERE

You can graph the minimum measurable settling time for a given resolution (Figure 20). Sample-command-path delays and sample-gate switching-residue profiles impose speed limitations on the circuit. You can measure settling time below 160ns at 16-bit resolution. For smaller signals, the sample gate’s switching-residue profile dictates an increased minimum measurable settling time of 265ns at 20 bits. The DAC/amplifier, summing resistors, and residue amplifier/sampling switch impose circuit-noise limitations. Resolution beyond 15 ppm requires you to use filtering or noise-averaging techniques. You can drive the 74HC123’s B2 input with a phase-advanced version of the pulse-generator input to largely eliminate sample-command-path-delay-induced error. This approach considerably improves minimum measurable settling time. You must use careful construction techniques and proven diligent measurements (see sidebar “Settling-time-circuit performance verification”).


FIGURE 20 HERE

Circuit application
It is good practice to “walk” the sampling window backward in time from the settled region to the last 100µV or so of amplifier movement so that you can observe the cessation of ringing. The sampling-based approach provides this capability and is a powerful measurement tool. Slower amplifiers may require extended delay, sampling-window times, or both, necessitating larger capacitor values in 74HC123 one-shot timing networks. Noise is the fundamental measurement limit with an unfiltered bandpass (Figure 21). The DAC (Trace B) settles to 16 bits, 1.7µs after Trace A’s time-corrected input step. The DAC amplifier’s compensation capacitor affects settling time (see sidebar “DAC-amplifier compensation”). Sample-gate feedthrough is undetectable, indicating that higher resolution is possible without overdriving the oscilloscope. Reducing the measurement bandwidth to 250 kHz attenuates noise (Figure 22). The 18-bit, or 4-ppm, settling requires approximately 5µs. The reduced bandwidth permits higher resolution, although the indicated settling time is likely pessimistic due to the filter’s lag. Decreasing bandwidth to 50 kHz permits 19-bit, or 2-ppm, resolution with an indicated settling in 9µs (Figure 23). The same filter that permits high resolution also creates a longer settling time.


FIGURE 21

FIGURE 22 HERE

FIGURE 23 HERE

You can use noise-averaging techniques to measure settling time to 20 bits, or 1ppm (10µV), without the time penalty of a bandlimiting filter (Figure 24). You can adjust the DAC amplifier for overdamped, underdamped, and optimum responses. Using averaging eliminates noise, permitting you to determine settling time due to DAC dynamics. In this case, settling time ranges from 4 to 6µs, and fractional LSB (least-significant-bit) tailing is evident. This measurement determines DAC settling time due solely to dynamics that a step input initiates. For this reason, you can consider averaged results academic. Noise limits the measurement certainty at any given instant to 100µV. It is reasonable to maintain that this noise means that the DAC never settles inside this limit. The averaged measurement defines settling time after you remove noise limitations.

FIGURE 24 HERE


Author Information
Jim Williams is a staff scientist at Linear Technology Corp, where he specializes in analog circuit and instrumentation design. He has served in similar capacities at National Semiconductor, Arthur D Little, and the Instrumentation Laboratory at the Massachusetts Institute of Technology (Cambridge, MA). A former student at Wayne State University (Detroit), Williams enjoys sports cars, art, collecting antique scientific instruments, sculpture, and restoring old Tektronix oscilloscopes.

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Components for 18-bit digital-to-analog conversion
Components suitable for 18-bit digital-to-analog conversion are members of an elite class (Table A). Eighteen binary bits is one part in 262,144—just 0.0004 percent, or 4 parts per million. This mandates a vanishingly small error budget, and the demands on components are high. The LTC2757 digital-to-analog converter listed in Table A uses Si-Chrome thin-film resistors for high stability and linearity over temperature. Gain drift is typically 0.25ppm/°C, or about 4.6 LSBs (least significant bits) over 0 to 70°C. Some amplifiers shown contribute less than 1-LSB error over 0 to 70°C, with 18-bit DAC-driven settling times of 1.8µs available. The references offer drifts as low as 1 LSB over 0 to 70°C, with initial trimmed accuracy to 0.05 percent.

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DAC-amplifier compensation
A number of practical considerations arise when you need to compensate a DAC-amplifier pair for the fastest settling time. Settling-time components include delay, slew, and ring times (Figure A). Delay, a small term, is due to propagation time through the DAC amplifier. The amplifier’s maximum speed sets the slew. Ring time defines the region in which the amplifier recovers from slewing and ceases movement within some defined error band. Once you choose a DAC-amplifier pair, you can readily adjust only the ring time. Because slew time is usually the dominant lag time, it is tempting to select the fastest-slewing amplifier available. Unfortunately, fast-slewing amplifiers usually have extended ring times, negating their brute-force speed advantage. The penalty for raw speed is, invariably, prolonged ringing, which you can damp only with large compensation capacitors. Such compensation works but results in protracted settling times.

The key to good settling times is to choose and properly compensate an amplifier with the right balance of slew rate and recovery characteristics. This task is harder than it sounds because you cannot predict or extrapolate amplifier settling time from any combination of data-sheet specifications. You must measure it in the intended configuration. A number of terms, including amplifier slew rate and ac dynamics, DAC output resistance and capacitance, and the compensation capacitor, combine to influence settling time. These terms interact in a complex manner, making predictions hazardous.

If you replace the DAC’s parasitics with a purely resistive source, you still cannot easily predict the amplifier’s settling time. The DAC’s output impedance further complicates a difficult problem. The only available approach for dealing with all these issues is to use a feedback-compensation capacitor. Its purpose is to roll off amplifier gain at the frequency that permits the best dynamic response. Normally, the DAC’s current output unloads directly into the amplifier’s summing junction, placing the DAC’s parasitic capacitance to ground at the amplifier’s input. The capacitance introduces a feedback phase shift at high frequencies. This shift forces the amplifier to “hunt” and ring about the final value before settling.

DACs have different values of output capacitance. CMOS DACs have the highest output capacitance—typically, 100pF—and it varies with the digital input code. The best settling results when you select the compensation capacitor to functionally compensate for all the parasitics (Figure B). Trace A is the DAC input pulse, and Trace B is the amplifier’s settle signal. The amplifier comes cleanly out of slew and settles quickly.

If the feedback capacitor is too large—27pF, for example—settling is smooth, although overdamped (Figure C). A 300ns penalty results. If the feedback capacitor is too small—15pF, for example—it causes an underdamped response with excessive ring time (Figure D). The settling time increases to 2.8µs. Note that these compensation values for 18-bit settling do not necessarily indicate results for 16 or 20 bits. You must establish optimal compensation values for any desired resolution. Typical values range from 15pF to 39pF.

DAC, amplifier, and compensation-capacitor tolerances become irrelevant when you individually trim feedback capacitors for optimal response. If you don’t use individual trimming, you must consider these tolerances to determine the feedback capacitor’s production value. DAC capacitance, DAC resistance, and the value of the feedback capacitor affect the ring time. The relationship is nonlinear, although some guidelines exist.

The DAC’s impedance terms can vary by ±50 percent, and the feedback capacitor is typically a ±5 percent component. Additionally, amplifier slew rate has a significant tolerance, which the data sheet lists. To obtain a production-feedback-capacitor value, determine the optimum value by individual trimming with the production-board layout. The board layout’s parasitic capacitance also counts. Then, factor in the worst-case percentage values for the DAC’s impedance terms, slew rate, and feedback-capacitor tolerance. Combine this information with the trimmed capacitor’s measured value to obtain the production value. This budgeting is perhaps unduly pessimistic but will keep you out of trouble. A defensible compromise may be rms (root-mean-square) error summing.

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Settling-time measurement of serial DACs
Measuring the settling time of serially loaded DACs requires additional circuitry. This circuitry must provide a start pulse to the settling-time-measurement circuit after serially loading a full-scale step into the DAC. Mark Thoren, applications-engineering manager for mixed-signal products at Linear Technology, designed and constructed a processor-based circuit that performs this task (Figure A). The start pulse (Trace A in Figure B) initiates the measurement. Traces B, C, and D are (chip select)/LD (load), SCK (serial clock), and SDI (serial data in), respectively. You measure Trace E, the resultant DAC output, for settling time in the usual way. Listing 1 provides the complete processor-software code.

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Delay and circuit-trimming procedures
The settling-time circuit uses an adjustable delay network to correct the input pulse for delays in the signal-processing path. Typically, these delays introduce errors of a few percentage points, so a first-order correction is adequate. Setting the delay trim involves observing the network’s input-to-output delay and adjusting for the appropriate time interval. Determining the appropriate time interval is somewhat more complex. Measuring the settling-time circuit’s signal-path delay involves modifications (Figure A). These changes lock the circuit into its sample mode, permitting an input-to-output-delay measurement under signal-level conditions similar to normal operation. In Figure B, Trace A is the pulse-generator input at 200µV/division. Note that a 10-kΩ/1Ω resistor divider feeds the settle node. Trace B shows the circuit output at A4, delayed by about 44ns. This delay is a small error, but you can readily correct it by adjusting the delay network for the same time lag. If you use a serial-DAC interface, you should add 10ns to the delay correction. Similarly, if you use a postamplifier, you must increase the delay correction by 17ns.

Use the following procedure to trim the settling-time circuit for optimum performance. You should make sure to perform these steps in order.

1. Turn off the input pulses.
2. Trim the “baseline zero” for 0V output at the oscilloscope at 10mV/division or less.
3. Disconnect the precision 10-kΩ resistors and the ground-settle node through the 5.1-kΩ unit.
4. Set the sample delay to midrange and the sample-window width to minimum.
5. Drive the pulse-generator input with a 40-kHz square wave.
6. Adjust the “sample interval zero” for no offset between the sample interval and the unsampled baseline.
7. Adjust the “sample-transition-purity” and “aberration” trims for minimum amplitude disturbances when the sample gate opens with oscilloscope horizontal at 50ns/division and the vertical sensitivity of 10mV/division.
8. Reconnect the precision 10kΩ resistors and remove the 5.1-kΩ unit from the settle node.
9. Adjust the delay compensation for a 44ns delay from the pulse generator input to the time-corrected output pulse.
10. Turn off the input pulses. Disconnect the pulse generator and its 50Ω termination. Apply 5V dc to the pulse input.
11. Connect Figure C’s network to the settle node. The added components shown furnish a 250µV-dc gain-calibration source when you replace the input pulses with a 5V level. Under the figure’s conditions, the DAC assumes a 10V output with the 5.1kΩ resistor mimicking the 10-kΩ divider’s output impedance at A1. You adjust the gain trim for a 10mV-dc deflection at the oscilloscope. This step completes the trimming procedure, and the circuit is ready for use.

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Settling-time-circuit performance verification
Prudent investigation requires a performance verification of the testing method. Performance verification for the settling-time test circuit requires a high-purity pulse generator that quickly transitions and settles to 1 ppm (part per million). This requirement is a difficult one, and I am unaware of any electronic means of achieving this capability.

Fortunately, electromechanical technology offers a viable technique. You can use a mercury-wetted reed-relay pulse generator (Figure A). Theoretically, when the contacts open, an infinitely fast falling edge appears across the 50Ω termination with zero settling time to 0V. In reality, this action does not take place (Figure B).

A typical commercial relay shows a less-than-5ns transition with a 500MHz ring-off of greater than 10ns. These imperfections are not surprising when you consider the parasitic terms (Figure C). Figure A’s deceptively simple schematic has a number of unintentional terms, including parasitic resistance, inductance, and capacitance and undesirable field interaction within the relay, which severely limit performance. Additionally, the connection through the relay to the output terminal constitutes an ill-defined transmission line, which promotes additional vagaries. The parasitic terms interact in a haphazard and unpredictable way, resulting in alien terms at the pulse output. The solution is to use a relay designed for inclusion in a wideband 50Ω system.

In the 1960s, Tektronix manufactured the Type 109 mercury-wetted reed relay for use as a pulse generator. In its preferred configuration, the relay switches energized charge lines into a 50Ω termination, resulting in a 250-psec rise-time pulse. This approach does not employ charge lines; rather, the device acts as a simple switch. The approach takes advantage of Tektronix’s exquisite care in manufacturing to make the relay transparent in a 50Ω system. A large-scale transition reveals an 800-psec fall time with a 1-GHz idth (Figure D). The actual fall time is probably somewhat shorter because the monitoring oscilloscope has a 350-psec rise time. The transition is singularly clean and devoid of discontinuities, with the exception of prefall corner rounding. Figure E shows sampling-switch techniques similar to the text’s to measure Type 109 relay fall-time purity to microvolts. The 109 relay’s output (Trace B) moves the final 220µV, settling inside 10µV approximately 265ns after the relay’s contacts open (Trace A). Actual 109 relay settling time may be shorter because the sampling circuit likely limits the measurement. Figure F shows a simplified version of the test circuit that produced these results. The Type 109 relay drives 20 cm of 50Ω GR-874 airline into a high-quality GR-874 50Ω termination at the clamped amplifier-sampling switch. The Tektronix pick-off components allow signal extraction from the airline without degrading transmission-line integrity. Note that using airline is a nonnegotiable requirement. The highest-quality Teflon 50Ω cable produces impure response, albeit minor.

It may be unrealistic for readers to duplicate the Tektronix 109-based results. The specified exotic apparatus is difficult and expensive to obtain, and the setup requires arduous labor and almost fanatical attention to detail. In this spirit, Figure G shows a “pretty good” mercury-wetted reed-relay pulse generator. Its performance, although falling well short of the circuit in Figure F, still furnishes a 10V step, which settles to 1ppm in 950ns. A simple clock (“resonance set”) furnishes low-frequency drive to the relay through the transistor-level shift and the LT1010 power buffer. The paralleled CMOS inverters provide trigger pick-off. You must use separate packages for the resonance-set and trigger functions to avoid output-pulse contamination. Figure H shows results for the pretty good step generator. Its slower settling and alien residue components compared with the Tektronix 109 approach are apparent. The event at the 10th vertical division is sample feedthrough-related gate turn-off.

Circuit calibration involves adjusting the resonance set until the relay emits a reasonably pure audible tone. Next, setting the 20V supply to a value that promotes the cleanest settling characteristics.

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Auxiliary circuits
Several auxiliary circuits are useful for DAC settling-time measurement. For example, you can use a simple, wideband, 10× preamplifier for oscilloscopes lacking the required sensitivity for 1ppm, 10µV settling-time resolution (Figure A). You should place this preamplifier directly at the oscilloscope’s input and connect it using 50Ω terminated BNC cable to the settling-time fixture output.

An autozero circuit locks the sample interval’s zero value to the nonsampled region’s baseline (Figure B). It eliminates the need for periodic readjustment of the sample-interval-zero trim when working at the highest levels of resolution over a protracted time. Synchronously switched A1 compares the sample interval’s and nonsampled region’s zero values and applies an appropriate offset, closing a correction loop around the LT1228. M1’s extended pulse precludes settling activity from influencing the sample interval’s zero value. The autozero-bias trim corrects for slight errors and should not require readjustment once you set it to equalize the sample interval’s zero value and the nonsampled region’s baseline. Figure C provides information for the autozero’s interconnection to the settling-time circuit. Signals include the time-corrected input pulse (Trace A), DAC output (Trace B), sample delay (Trace C), M1’s input (Trace D), M1’s sample-interval zero pulse (Trace E), G1’s sample command (Trace F), and settle signal’s output (Trace G). M1’s delayed output maintains the sample interval’s zero value independently of the settling signature.

You use a simple time calibrator to verify the oscilloscope’s timebase accuracy (Figure D). Q1 and Q2 form a 1-MHz quartz oscillator. The 74C90 provides switch-selectable output periods of 2 and 5µs, and the attenuator supplies 50Ω output impedance. The oscillator period is suitable for calibration points appropriate for expected DAC settling times. Other periods are available by varying the oscillator’s frequency, division ratio, or both. The 9V battery’s drain is approximately 10mA.

References
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28. Williams, Jim, "High Speed Amplifier Techniques: A Designer’s Companion for Wideband Circuitry," Application Note 47, Linear Technology Corp, 1991.
29. Type 109 Pulse Generator Operating and Service Manual, Tektronix Inc, 1963.
30. Williams, Jim, "Signal Sources, Conditioners and Power Circuitry," Application Note 98, "Wideband, Low Feedthrough, Low Level Switch," pg 13, Appendix A, "How Much Bandwidth is Enough?" pg 26, Linear Technology Corp, November 2004.
31. Williams, Jim, "Applications Considerations and Circuits for a New Chopper-Stabilized Op Amp," Linear Technology Corp, Application Note 9, March 1985.


Captions
Figure 1: DAC settling time components include delay, slew, and ring time. Fast ampli¬fiers reduce slew time, although longer ring time usually results. Delay time is normally a small term.
Figure 2: A popular summing scheme for DAC-settling-time measurement provides misleading results. An 18-bit measurement causes a more-than-800-times increase in oscilloscope overdrive.
Figure 3: This arrangement eliminates oscilloscope overdrive.
Figure 4: Conventional choices for sampling switches include JFETs (a), MOSFETs (b), and diode bridges (c).
Figure 5: Some low-feedthrough electronic-switch equivalents (a and b) are difficult to implement. You must optimize one practical scheme for low feedthrough on rising and falling control-pulse edges (c). In another, inherent bandwidth reduction minimizes falling-edge feedthrough (d).
Figure 6: This transconductance amplifier switch has minimal control-channel feedthrough.
Figure 7: A low-level, 100-MHz switch has minimal control-channel feedthrough.
Figure 8: The control input (Trace A) dictates a switch output’s (Trace B) representation of a 0.01VDC input. The control-channel feedthrough settles in 20ns. Turn-off feedthrough is undetectable due to deceased signal-channel transcon¬ductance and bandwidth. The aberration capacitance is 35pF for this test.
Figure 9: For a 0V signal input, the output (Trace B) peaks at 0.005V before set¬tling to 0.001V 40ns after the switch-control command (Trace A). Aberration capacitance is 35pF for this test.
Figure 10: The aberration capacitance is 0 pF; otherwise, conditions are identical to those in Figure 9. The feedthrough-related peaking increases to 0.02V, and the 0.001V settling time remains at 40 nsec.
Figure 11: The signal-channel rise times for 0 pF (left trace) and 35 pF (right trace) are 3.5 and 25 nsec, respectively. The switch-control input is high for this measurement.
Figure 12: You can combine the electronic switch with the DAC-amplifier summing method.
Figure 13: A detailed DAC-settling-time-measurement circuit closely follows that of Figure 12. Optimum performance requires atten¬tion to layout.
Figure 14: The settling-time-circuit wave¬forms include a time-corrected input pulse (Trace A), a sample command (Trace B), a DAC output (Trace C), and a settling-time output (Trace D).
Figure 15: A poor sample-interval zero adjustment causes a shifted output base¬line (Trace B) during Trace A’s sample interval.
Figure 16: A trimmed sample interval’s zero adjustment has no output baseline deviation (Trace B) during the sample interval (Trace A). The sample command’s feedthrough is just visible at Trace B’s leading edge.
Figure 17: The output response (Trace B) to a sample command’s turn-on (Trace A) before you trim out aberrations and transi¬tion purity has a signal delay of 20ns. The aberrations peak at 350mV and settle in 50ns. You ground amplifier A1’s posi¬tive input using a 5kV resistor for this figure and Figures 15 and 16.
Figure 18: Trimming improves the out¬put response (Trace B) to a sample command’s turn-on (Trace A). The delay increases to 70ns, but aberrations peak at only 50mV, and the circuit settles in 50ns.
Figure 19: The output response (Trace B) to the sample command’s turn-off (Trace A) shows a 1000-to-1 transconductance drop, ensuring a clean transition, indepen¬dent of the trim state.
Figure 20: The sample-command-path delays and sample-gate-setting profile impose the minimum measurable settling-time-versus-resolution limits. Achieving a resolution beyond 15 ppm requires filter¬ing or noise averaging.
Figure 21: The 0 to 10V DAC with an unfiltered bandpass settles (Trace B) to 16 bits, or 15ppm, in less than 2ms after Trace A’s time-corrected input step. The sample gate’s feedthrough is well-controlled, indicating that higher resolu¬tion is possible without overdriving the oscilloscope. Noise is the limitation for this measurement.
Figure 22: Reducing the measurement bandwidth to 250kHz attenuates noise. The settling to 18 bits, or 4ppm, requires approximately 5ms. Filtering permits increased resolution, although the indi¬cated settling time increases.
Figure 23: You can discern 19-bit, or 2ppm, settling 9ms after the input com¬mand with a 50kHz bandwidth.