100-mm graphene wafers target next-generation electronics

Researchers at the EOC (Electro-Optics Center) at Pennsylvania State University’s Materials Research Institute have produced 100-mm-diameter graphene wafers. Using silicon sublimation, EOC researchers David Snyder and Randy Cavalero thermally processed silicon-carbide wafers in a physical-vapor-transport furnace until the silicon migrated away from the surface, leaving behind a layer of carbon that formed into a one- to two-atom-thick film of graphene on the wafer surface.

The researchers are initially focusing on graphene materials to improve transistor performance in various RF applications, with Penn State developing graphene-device processing to enhance graphene-transistor performance. The university has also fabricated RF FETs on 100-mm graphene wafers. The researchers plan to improve the electron mobility of the silicon-sublimated wafers to nearer the theoretical limit, which is approximately 100 times faster than silicon.

The researchers are also using a nonsublimation approach to developing synthesis and device fabrication of graphene on silicon as a means to achieve wafer diameters exceeding 200mm.

Pennsylvania State University - Materials Research Institute
www.mri.psu.edu

Caption
This 100-mm graphene wafer contains approximately 75,000 devices and test structures. The inset shows an optical image of a single chip. Each small square pad on the chip measures 100 microns (courtesy Pennsylvania State University).