Less integrated PMIC decreases design complexity, increases reliability and flexibility

Each new generation of portable battery powered electronic products brings a new level of integration. People are always looking for a smaller but more feature rich handset that integrates more gadgets, but, on the other hand, they naturally don’t want to sacrifice battery life time and keep it as long as possible.

Semiconductor technology has to provide handset designers with more sophisticated power management solution. One of the trends is to integrate more and more functions in the power management IC (PMIC) with many voltage regulators, DC/DC converters as well as any other power management related functions in a single chip. System-wise, it can also make sense to integrate audio CODEC and amplifiers as well as any other non-RF related analog functions.

This approach offers to designers of portable electronic systems a “three-chip” highly integrated solution resulting in highly integrated system core. At first order, main advantages of this solution are low components count, cheap bill of material (BOM) content and highly reliable manufacturing. This seems a logical approach to save space and cost, but is it always feasible and the best option?

Several potential drawbacks that may lead to different integration schemes have to be considered:
• Besides power consumption and power dissipation related potentials issues, designers should also very carefully layout the power rails and consider the optimal localization of power generation functions on the PCB.
• From marketing and sales stand point, the most important parameters are design cycle time and platform flexibility. Clearly, highly integrated solutions are not flexible enough to accommodate feature rich functions modifications required by versatile market trend and could not always cope with short design cycle time.

Integration considerations
Lithium ion batteries (Li-ion) offer operating voltage range from 2.8V ~ 3V up to 4.2V. Usually, a system powered by this cell switches off when voltage drops down to about 3.3V to keep enough headroom and avoid highly depleted battery safety issue.

The logical and straightforward way to optimize battery life time would be increasing its size. But, as power density does not improve as fast as the market expects, this would also directly impact handset size. Consumers would not pay the price of extra size for extra features such as video, audio, gaming, or Global Positioning System (GPS), for instance.

The designer clearly has no choice but to carefully manage handset power usage in order to save battery life and keep it at least as long as the user was used to with the previous generation. Another option a designer can consider is to extend the battery operating range, nibble away at the low voltage safety margin, and operate the system at a voltage lower than 3.3 V.

It leads to more sophisticated power management technique and to increase amount of power domains the electronic will work in. It is achieved at the price of higher complexity and higher cost, especially if this is implemented with off-the-shelf highly integrated PMICs.

Constraints, such as PCB real estate on which designers can place components, cost, and manufacturing could drive the use of highly integrated ICs. But this approach brings up additional design challenges, to make sure that the best performances are achieved. Mainly thermal management and signal routing have to be considered and, depending on the application, may lead to use a separate IC on top of the main PMIC. It could lead to a different level of integration with a sub-system partitioning approach.

Thermal management
When using very highly integrated ICs, designers should be aware that the package maximum power dissipation is much lower than the potential power the silicon may have to evacuate to remain in an acceptable temperature range when all regulators are operating at their maximum current.

For instance, let’s consider the handset main power functions supplied by a highly integrated PMIC. It integrates two 90-percent average efficiency DC/DC converters, five LDOs and a white LED driving boost converter able to supply five LEDs in series with 85 percent average efficiency, plus other functions such as other DC/DC or regulators for extra functions, battery charger, audio ADC/DAC, and power stages. Now, considering this system is supplied by a typical Li-ion 3.6V voltage, let’s evaluate the IC dissipation when power supply functions are turned on and battery charger and audio functions are turned off.

Table 1: Power supply system.



Table 2: Power dissipated in each element in a PMIC.



Most of the PMICs are provided in BGA or QFN package. Whatever the package is, the central area is usually connected to the PCB ground plane in order to evacuate out of the package as much power as possible and keep the silicon temperature in an acceptable range. With this technique and optimized PCB layout, the package thermal resistance (RθJA) can be as low as 40ºC/W.


Thermal characteristic of a BGA64 package.


If we consider again the previous example, the worst case power dissipation with just the main processor regulators operating at maximum current, silicon temperature elevation will be about 90ºC, bringing it up to maximum operating condition for 35ºC ambient temperature. This may lead to system failure for normal operating temperature range. Thermal management increases dramatically the design complexity, requiring the designer to calculate and continuously monitor the maximum heat that the PMIC will have to dissipate. This has influence component placement as thermal failure may weaken solder joints and also affect nearby components’ operation and integrity.

Even if the thermal management concerns are kept under control, in some special use cases the IC power supply functions may dissipate too much heat. Then, other functions should be, in the worst case, turned off, or, at least, switched into a “heat save” mode with lower performances. In most cases, the user would not understand this sacrifice and this situation should be avoided as much as possible.

Depending on the system specification, one solution to help solve thermal issues would be splitting the large PMIC into several smaller ICs or separating high dissipation regulators and putting them into a sub-PMIC. For a mobile phone that integrates video and gaming functions, the designer may find benefit in supplying each module by an independent sub-PMIC controlled by the main processor.

If the main PMIC power dissipation is still too high, designers can consider also putting other analog functions (audio power stages and ADC/DAC, display supply) in a separate “heat safe” sub-system IC to avoid the “heat save” mode.

Location on the board
The size and viewing quality of displays have greatly improved during the past few years. In line with the increasing display sizes, the space available inside the handheld device also gets bigger and the location of functions can be quite far away from the main PMIC.

Apart from that, the parasitic components related to the PCB layout will become more predominant. Consider the DC/DC converters from the previous example supplying a processor located 5cm away from the PMIC, connected with a 5mΩ/mm track. The parasitic resistance will be 250mΩ and voltage drop in the parasitic resistance will be 250mV under 1A and 125mV under 500mA.

If the processor core power supply level of 1.2V ±5 percent is to operate at maximum clock frequency, the 125mV drop corresponds to about 10 percent of the operating voltage and even for half of the maximum current, and the voltage at the processor edge will be out of its operating range.

To overcome this issue, the designer has several options:
1. Set the DC/DC converter output voltage higher than the processor typical operating range to compensate for this drop. Considering dispersion between components, this is risky option.
2. Connect the converter feed back node as close as possible to the processor. Drop will be automatically compensated. However, feedback pin is a high impedance input and prone to pick up a lot of noise.
3. Use of a separate sub-PMIC to supply this processor as well as related hardware. This makes design more flexible and simplifies layout.

Of course, the third option increases the BOM and manufacturing costs, but it leads to higher reliability, simpler design and better flexibility.

In the handset, we cannot get away from using a highly integrated system as a core function. However, other considerations such as reliability, heat dissipation and longer-than-optimized PCB tracks could make integration benefits less clear. In addition, poor flexibility, long IC and chipset development cycle time, as well as differentiation requirements from manufacturers will require other solutions.

Separate subsystems can be good alternative—they will combine the advantage of integration and simple design with high flexibility and improved reliability. Assuming that the silicon vendors can provide cost-effective, compact and highly efficient solutions, the handset designers will have a number of choices in selecting the more appropriate solution and accommodating time-to-market pressures with reliable and time constrained design.


Author Information
Jacques Lavernhe is a system engineering manager at ON Semiconductor.