Low-power Dual-edge Triggered Flip Flop Implementation Using Single-edge Triggered Flip Flop

A low power implementation of Dual Edge Triggered Flip Flop (DET FF) has been proposed in the paper. In addition to inherent advantage of using a DET-FF, i.e. low power dissipation in clock network due to requirement of lower frequencies, the proposed DET-FF exploits the low data toggling activities to reduce the power consumption inside a DET-FF. Circuit simulations show that considerable reduction in power dissipation is possible if input data signal has low toggling activity and this characteristic is exploited to control the clocking to a sequential element.

Introduction
The three main problems which are faced by VLSI design based on digital circuits involving state machines are increasing clock frequency requirements, low power implementation and utilizing minimum area for implementation. Dual Edge Triggered Flip Flops (DET-FF) have emerged as one of the techniques by which we can reduce the clock network frequency and hence save on the switching power in the whole clock network. This is made possible by data capture on both positive and negative edges of the clock. Multiple implementations of DET-FF [1,2,3,4] are available which have varying characteristics which have been compared in detail in a paper by Chung et al [5].

In addition to the inherent advantages of the DET-FF, an additional feature of the data signal toggling activity can be exploited to come up with a scheme which can result in further power savings. Such schemes have been discussed in ample detail for single edge triggered flip flops by Strollo et al [6]. The input data activity has been observed to be typically up to 20 percent of the clock toggling activity and this property can be exploited to achieve the low power targets.

In this paper, a novel DET-FF circuit will be presented. Proposed FF uses comparison logic to sense data toggling to reduce power consumption inside the sequential circuit elements. Also the proposed implementation uses a single edge triggered flip flop (SET-FF) to reduce area overhead which is introduced by DET-FF usage.

Basic dual edge triggered flip flop
The existing DET-FF circuits follow similar implementation techniques involving transmission gate, latch and mux based structure. Each of the positive and a negative level latches capture data on both edges of the clock which is transferred to output circuit based on the clock edge i.e. positive or negative edge. The point of concern here is the continuous switching of the cross coupled inverters which form the latches for positive and negative levels. This results in unnecessary power dissipation in the circuit even when the data is not toggling and increases the total power requirements of the design. One of these implementations is demonstrated in Fig 1.



Power consumption
If the power consumption of this circuit is analyzed, we find that Pckt = V2 {fclk C1 + fdata C2 }.

Here fdata is the average data toggling frequency and fclk is the input clock frequency. Depending upon the input clock toggling, this factor of clock related power dissipation can be reduced by applying selective clocking and hence reducing the power dissipation in the circuit. This can be achieved by using data as the sensing signal to control the clocking scheme for the sequential circuit and hence limiting the clock frequency proportional to the data frequency.

Proposed Circuit
The proposed circuit illustrated in Fig. 2 is the DET FF which has the feature to sense the data change and according to this, generate an enable signal for the clock controlling logic and hence reducing the effective clock frequency.







OPERATION OF CIRCUIT
Fig 2c shows the basic single edge triggered flip flop which is used for capturing the data at both positive and negative edges which is controlled by the ckff , the effective clock. This ckff is controlled by clock controlling logic stage1 and stage2 shown in Fig2A and Fig2B.

Comparison Logic : This logic tries to compare Data_input and Q. Enable(en) is asserted whenever Data_input is different from Q. This enable(en) is used to generate enable_bar (enb) signal. Both “en” and “enb” are used to decide if clock (ck) should be propagated internal to the flop.

Clock Controlling Logic-Stage1: Using the “en” and “enb” generated by Comparison Logic, it is decided if the clock should propagate through the shown transmission gate. When en==0, transmission gate passes the clock then clock passes, but the tri-state buffers are not conducting (since en==0). cklatch and cklatch_b would hold their value. When en==1, transmission gate stops conducting, and the tri-state buffers start conducting and a hence the latch in Stage1 would be enabled.

Clock Controlling Logic-Stage2 : Based of “en”, ”enb”, “cklatch”, “cklatch_b”, it is decided which phase of the clock needs to be propagated. The stable ckff state is maintained in case the clock is not generated due to a stable data input for multiple clock cycles.

RESULTS
The circuit was simulated using 90nm technology components and the frequency of operation was 150MHz. The timing diagram shown illustrates the circuit operation. The shaded portions show the clock edges at which the effective clock ckff was not generated. This is where the circuit achieves the power conservation by controlling clock to the sequential part of the circuit and making most the nodes of clock controlling logic constant, hence saving dynamic power in most of the circuit.

The clock edges before which a data toggle happens, the ckff pulse is generated and is supplied to the SET FF for the capture operation. This is done regardless of the clock edge. The circuit shows correct operation in both the cases, one where data toggling activity is equal to clock toggling activity and the other when the data switches intermittently. The power saved is directly dependent on the data toggling factor and hence varies according to input vector to the state machine in which the proposed circuit is used. While analyzing the 33 percent duty cycle case, the savings achieved were more than 70 percent in 90nm node.




REFERENCES
[1] S.L. Lu and M. Ercegovac, “A Novel CMOS Implementation of Double-Edge-Triggered Flip-Fiops”, IEEE J. of Solid-state Circuits, August 1990, pp. 1008-1010.
[2] A. Gago, R Escano & J.A. Hidalgo,“Reduced Implementation of D-type DET Flip-Flops”, IEEE J. OfSolid-State Circuits, March 1993, pp. 400-442.
[3] RHossain, L.D.Wronski & A.Albicki, “Low Power Design Using Double Edge Triggered Flip-Flops”, IEEE Trans. on VLSI Systems, June 1994, pp. 261-265.
[4] M. Sachdev, “ IDDQ and Voltage Testable CMOS Flip-flop Configurations”, Proc. ITC 1995, pp.534-543.
[5] A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops, Wai Chung; Lo, T.; Sachdev, M. Very Large Scale Integration (VLSI) Systems, IEEE Transactions.
[6] A.G.M. Strollo, E. Napoli, D. De Caro. New Clock-Gating Techniques for Low-Power Flip-flops.
[7] R. P. Llopis, M. Sachdev, “Low power, testable dual edge triggered flip-flops”, ISLPED Dig. of Tech. Papers, p.341-345, 1996.