Uncertainties abound at 22nm

Designers have made a number of predictions for getting at 22nm. Some of the issues hotly debated are whether to change from a planar CMOS structure to multi-gate, from tungsten to copper plugs, and to alternative channel materials. These changes are drastic, risky, and costly. Designers generally agree that these should be brought about only if absolutely necessary. Now with significant progress made toward 22nm—Intel says that it is on the way to introducing 22nm products in 2011—there are still uncertainties as to which are the best design methods to approach 22nm.

Planar technology
Intel confirms that at 22nm it will stay on to planar bulk technology. This ends speculation that Intel will go vertical with a tri-gate transistor at this node. Intel’s 22nm test chip has SRAM arrays, logic peripheral circuits, 364Mb array size, and 2.9 billion transistors. It has third-generation gate-last high-K/metal gate process that deposits both the dielectric and the metals at the end of the process. However, Intel is not optimistic that planar bulk technology can be extended further to 15nm. The company is still working on the process architecture for this node, though there is at least one report that Intel will adopt a multi-gate, possibly tri-gate, architecture.

Thinning the gate dielectric with high-K materials has been commonly adopted as designs moved on to 65nm and below. The process has worked well hitherto. But at 22nm the gate dielectric is not thinning to the extent designers need to bring about the required improvement in gate length scaling. Operating voltages are levelling off, thus increasing difficulties in reducing power consumption that is among the greatest challenges designers face today. Making the junctions shallower does not help, because it is found to increase the source/drain resistance.

While Intel says that further invention will be needed beyond pitch and gate length scaling to tackle the problems, some reports suggest that doping is increasingly being looked upon as a method to solve many of the problems at 22nm. To avoid short channel effects, more phosphorous and boron are being doped into the channel. However, this increases threshold voltages and reduces transistor speed. Random dopant fluctuations have a significant impact upon threshold voltages, adversely affecting performance and lowering yield.

Depletion
Fully depleted (FD) or partly depleted (PD) technologies are also being worked upon. Intel confirms of the inherent low-power advantages of FD technologies. Among options Intel is exploring are tri-gate devices and FD planar technologies. How far will SOI go into easing the problems? There are contradictory reports. Intel does not seem to be enthusiastic about SOI for partially depleted, planar CMOS because Intel believes this has not given it the anticipated extra performance or lower power. However, Global Foundries, which has announced that it is working on FD CMOS without specifically mentioning at which node it will transit to such a CMOS, is supporting SOI roadmap. The Fishkill Alliance seems to be working on multiple architectures simultaneously. SOI is one of them.

In the conflict between doping and FD, designers seem to be gradually veering round to the view that when getting a consistent amount of doping in the channel becomes difficult to manage, FD architecture should provide the better choice. IBM is likely to use FD technologies at 22nm for its MPU. It is working on FD transistors, using planar structures on extremely thin SOI. IBM reports that such SOI, with its thin silicon body, reduces short channel effect problems arising from scaling the extensions to below the depletion width.

While both FD-SOI and PD-SOI are being worked upon, it seems that Intel will continue to shun SOI in the foreseeable future while IBM will push it hard. Again, Intel seems to be stretching bulk wafers while IBM seems to be moving to FD SOI.