PMC Goes Multicore with RAID Controller

Multicore SOC (system-on-chip) architectures are gradually seeking out the spectrum in which no other way exists to reach the desired performance level, but also in midrange applications, in which several small cores can be cheaper and more energy-efficient than one fire-breathing CPU. Consequently, embedded-application developers are wrestling their code into multiple threads, and SOC developers are providing cores to match the threads.

A case in point, as PMC-Sierra recently announced, is a RAID (redundant-array-of-inexpensive-disks) controller. This application might not seem computationally intensive, but, as Cameron Brett, PMC-Sierra's product-marketing manager, points out, the plummeting price of NAND flash is changing the picture.

Consider a high-performance RAID of, say, 20 rotating drives. If you want perform¬ance, you will use the drives in short-stroke mode-that is, employing only the outermost tracks, on which the data rate is highest and you can minimize seek time. That approach gives you good performance, but you use less than 10 percent of each drive's raw capacity. For about the same price, you could get four 100GB solid-state drives, connect them in a RAID configuration, and get about 300GB of usable capacity. The solid-state drives would slash your power consumption from more than 200W to about 10W, however, and they would increase available throughput from about 9000 to approximately 90,000 IOPS (input/output operations per second). Suddenly, the performance of the RAID controller is an issue.

PMC has responded with a new line of RAID-controller ICs, a joint development with IBM to produce a multithreaded version of IBM's RAID firmware stack, and a low-profile, eight-lane PCIe (Peripheral Component Interconnect Express) Generation 2 card to plug into x86 servers. The products target use in RAID configurations of solid-state drives, as well as conventional hard-disk-drive RAID arrays, using either SATA (serial advanced-technology attachment) or SAS (serial attached small-computer-system interface), including the 6-Gbps SAS generation, so the controller must deliver performance. "Each solid-state drive is capable of 15,000 to 30,000 IOPS," says Zaki Hassan, PMC's director of product marketing. Even with a four-drive array, this rate is significant.

To support the RAID stack at this throughput, PMC clusters three multithreaded MIPS 34k cores around a high-speed switch. The chip uses only local memory without external DRAM, Brett says. The board that uses the chip, the BR5225-80, measures in at more than 136,000 IOPS on 4000 random reads, and more than 44,000 IOPS on the 4K OLTP (online-transaction-processing) random 2-to-1 metric. Additionally, the chip supports one end of a Web-accessible, SMI-S (Storage Management Initiative Specification) 1.4-compliant management utility that runs on the host server.

PMC-Sierra
Caption
PMC-Sierra’s new line of RAID-controller ICs, a joint development with IBM, features a multithreaded version of IBM’s RAID firmware stack and a low-profile, eight-lane PCIe Generation 2 card to plug into x86 servers.