Ultra Low-power High-speed Pipeline ADC in 65nm CMOS

By Pratap Narayan Singh, Ashish Kumar, Chandrajit Debnath, and Rakesh Malik, STMicroelectronics India

ADCs (analog-to-digital converters) are the most common analog components used in numerous electronics applications. Speed requirements of ADCs vary from a few kHz to GHz and resolutions vary from 6b to 24b, depending on the application. Multiple architectures are used to implement ADCs with a wide variety of speed/resolution combinations and applications as shown in figure below. This article will focus on the need and realization of an ultra low-power “high speed data acquisition” pipelined ADC.


Fig. 1: ADC resolution vs. speed and application.

High-speed ADCs in low-power applications
High-speed ADCs are integral part of a variety of low power applications like wireless communication, medical instrumentation, data acquisition systems, etc. Battery operated wireless products require ultra low-power consumption to increase battery discharge time and battery life. Medical instrumentation and data acquisition systems can maximize the number of parallel analog channels with availability of low power, high speed ADCs. Hence, reducing power consumption of high speed ADCs is turning out to be need of the hour for the electronic industry. ADCs of 10b-12b resolution operating at 100MHz sample rate are most commonly used in numerous low power applications. To satisfy such requirement, an 11b 100Mhz ADC was developed in 65nm CMOS technology which consumes only 1.2mW power from 1.2V supply.

Pipelined ADCs are the most suitable candidate for realizing such speed and resolution. The main contributor of consumption in pipelined ADCs is the Operational amplifier.

Challenge
High-speed ADCs realized with 1.5b/stage and single stage operational amplifier are traditionally considered to be the most power optimal architecture in this category. In this architecture the maximum band width of operational amplifiers is scaled down by a factor of two (2) only in closed loop configuration and thus half of the bandwidth can be utilized. Also this architecture uses minimum number of comparators and offers very high tolerance for comparator offset. If the number of bits/stage is increased say to 2.5b/stage, the required number of operational amplifiers is less. But the available band width of the operational amplifiers is scaled down by a factor of 4 in closed loop configuration of 2.5b architecture implementation. Hence the available band width is actually half of what is available in 1.5b stage. To regain the similar band width, each operational amplifier has to be biased with more than double of the bias current. In addition to that, the no. of comparators are also increased in this architecture. Thus 2.5b/stage architecture does not offer any power advantage vis-a-via 1.5/stage if both are implemented using traditional single stage operation amplifier.

The best known low power 10b ADC published across journals and presented in conferences is consuming 4.5mW of power and is implemented using 1.5b/stage with single stage telescopic cascade operational amplifier (Boulemnakher, ISSCC February 2008).

The 4.5mW of power was definitely quite outstanding for ADCs with 10b resolution and 100MHz speed. But low power need from the product division is gradually becoming more and more demanding. Hence further reduction of power and reducing it to bare minimum level was necessary to gain substantial competitive edge in this extremely challenging market.

To achieve the challenging target, 2.5b/stage architecture was revisited. Going back to the basic architectural issue, it was observed that 2.5b/stage uses half the no. of amplifiers but its limitation is operational amplifier bandwidth reduction by a factor of 4. If bandwidth of the operational amplifier can be retrieved, 2.5b/stage would be more power optimal. An innovative technique was required to eliminate this particular challenge.

Achieving lower power
The first level of power reduction was achieved by sharing the operational amplifiers between consecutive stages. In traditional implementation, each stage uses a dedicated operation amplifier. But this amplifier is active in just one phase and inactive in reset phase. In this design the operational amplifier is shared between two consecutive pipelined stages working in two different clock phases and does not remain idle or inactive in any condition.


Fig. 2: ADC architecture.

The ADC architecture is shown in figure 2. After sharing the amplifiers and achieving a factor of power reduction, the focus was shifted to the operational amplifier. A two-stage operational amplifier was considered rather than a traditional single stage amplifier in order to address the bandwidth reduction aspect. Bandwidth and stability margins of single stage operational amplifier are normally governed by the load capacitance present at its output terminals. Moreover, common mode loop stability requires the differential loop also to be stable at unity gain even though, feedback factor of 2.5b stage requires stability at 12dB gain frequency. So when the operational amplifier is used in 2.5b stage, the bandwidth is simply reduced by a factor of four (4).


Fig. 3: Schematic of operational amplifier.

To overcome this limitation, a two stage operational amplifier was used shown in figure 3, composed of a telescopic cascode followed by a differential gain stage. The telescopic cascode stage need not sustain high signal swing at its output and hence its biasing requirement is not very stringent. Second stage being a simple differential gain stage can achieve 1.4Vpp-diff swing at supply voltage of upto 1V. Two gain stages are having independent common mode control and this configuration makes differential loop almost independent of common mode loops.

The differential loop can be separately compensated without impacting any of the common mode loops. Since in 2.5b/stage architecture the operational amplifier is always used with a feedback factor of 1/4, the operational amplifier needs to be stable with adequate phase/gain margin only at 12dB and not at 0dB gain. On the other hand the available bandwidth of the operational amplifier is also at 12dB gain frequency. In this operational amplifier, miller compensation technique was used which attains necessary stability margins of differential loop at 12dB gain frequency and maximizes the available bandwidth by maintaining the common mode loop stability. This technique is instrumental in reducing the power consumption and hence the overall ADC.

Success summary
Thus using a2.5b architecture and a two point approach, i.e sharing of OPAMP between consecutive stages and an innovative two stage amplifier which employs independent common mode loop for each stage eliminates the bandwidth reduction issue of 2.5b/stage. This makes the architecture most power optimal.

By using the approach, ADC constitutes of only two operational amplifier which consumes 400µA and 150µA respectively. So the DC power consumption of core ADC is 550µA only and remaining power is contributed by switching current.

Silicon micrograph and performance
The chip micrograph of the ADC is shown in Figure 4. ADC area is 0.05mm² with a dimension of 140x350µm.


Fig. 4: Chip micrograph.

Comparison of present work vs. publications
The ADC consumes total 1.2mW from 1.2V supply resulting in FOM of 15.6fJ/step. Figure of Merit (FOM) is defined as Power/2^ENOB*2*Band Width. The FOM achieved by the ADC is best reported so far. Performance summary and FOM comparison are shown in Figure 5.


Fig. 5: FOM comparison and performance summary.

Product integration
This ADC has been integrated in several low power wireless application ST products and is one of the premier designs coming from ST India. Till this article, it is known to be lowest power ADC in industry and among premier IEEE publications.