TSMC Tapes Out 28nm Chip Utilizing Synopsys Galaxy Implementation Platform

Synopsys Inc. has announced that TSMC has successfully taped out a complex 28nm Product Qualification Vehicle (PQV) test chip using Synopsys' Galaxy Implementation Platform. Key features used to design the PQV test chip include 28nm design rule support for place-and-route, interconnect process modeling, IEEE 1801-2009 (UPF)-based hierarchical low power flow, power-aware design-for-test (DFT) and advanced signoff capabilities. Synopsys tools exercised by TSMC in the RTL-to-GDSII implementation and signoff flow for this test chip development included DC Ultra RTL synthesis, IC Compiler physical implementation, PrimeTime SI timing signoff and StarRC Ultra parasitic extraction.

TSMC's complex 28nm test chip design consisted of more than 200 million gates of logic and memory combining multiple IP cores and custom designed blocks. The chip's multiple power and clock domains presented additional design challenges that were efficiently handled by the Galaxy platform tools. TSMC deployed advanced methodologies during the test chip design to address hierarchical power implementation, DFT, advanced routing rules and manufacturability compliance.

To address the design's multiple multi-voltage blocks, TSMC utilized the Galaxy platform's hierarchical low power flow, including power intent definition described with UPF. This approach enabled the engineering team to implement different sub-blocks of the design concurrently, resulting in faster overall time-to-results. In addition, the Galaxy tools were used to successfully deploy TSMC's pulsed latch approach to maximize power savings across the chip. To validate 28nm manufacturing compliance, TSMC used Synopsys' IC Compiler Zroute DFM-aware routing capabilities.

Synopsys

TSMC

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