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Japan Coalition to Take on Intel

( 01 Sep 2010 )
By Kirtimaya Varma, Editor-in-Chief, EDN Asia

CPU designers are likely to see a new paradigm in a year or two. For the first time, Intel may face a challenge to its global domination in CPU technology and market. Undoubtedly AMD has valiantly tried to confront Intel at least on the technology front. But AMD is so small compared to Intel that it had insignificant impact on Intel’s domination. Intel continues to hold over 80 percent market share in the overall CPU market and even higher in the key segments of mobile systems and servers.

UNPRECEDENTED
However, the Japanese chip makers, who have entered into an unprecedented coalition to design what they call a “super” CPU specifically to confront Intel, are reported to be progressing well. The coalition comprises of major players such as Fujitsu, Toshiba, Panasonic, Renesas, NEC, Hitachi, and Canon. Besides, the Japanese government is also funding the project with an initial capital of 3-4 billion yen. Obviously Intel will face a competitor that unlike AMD has huge resources, at least as huge as its own.

Some characteristics of the “super” CPU, set for release next year or in 2012, are now known, which should give Intel designers an idea of the direction in which their prospective competitor is working. The “super” CPU is being standardized in such a way that it could be incorporated into different brands of televisions, digital cameras, and other electronic appliances. Hironori Kasahara, professor of computer science at Waseda University, is the main designer. He has designed an energy saving software for the CPU. In the first stage, each company will produce its own CPU compatible with this software before designing the final chip. The application of this chip will be extended to automobiles, servers, and robot sectors.

The Japanese alliance, Intel, AMD, and other chip makers need to grapple with some common chip design issues. Perhaps the most debatable one is whether an inflection point has been reached in IC scaling? Some designers say that even as processes are getting expensive and technology problems becoming harder to solve, scaling can go on for another five to six years. But others believe that inflection point is in the near future, because performance and energy gains are not commensurate with the increasing costs of design.

Some designers argue that the issue is not merely scaling but adding new kinds of devices, such as sensors, actuators, and optical interconnect, to a conventional IC, and developing a true 3D IC technology. They contend that to make costs justifiable, the increasing diversity of technology applications should need more focus than whether scaling is at an inflection point.

IMEC seems to be more into new materials, ranging from germanium implants to III-V materials to graphene, which would not only make designs more cost effective but also take them beyond 15nm.

How good are ASIC designs for the future? Most designers share the view that the design costs are increasing so rapidly that to recover the cost of a design one will need to stick to a standard-product rather than go for ASICs.

ADVANTAGE
While the perspectives of the Japanese alliance are at present not known on most of the above issues, it is at a tremendous advantage in building a standard-product chip that can be used across applications. The “super” CPU has a built-in universal standard and software format for different appliances. This will save design costs for all electronic sectors where it is used. The mass scale of production enabled by the CPU’s wide application range could further reduce the product cost and make it more competitive against Intel.

With the enormous rise in chip design and production cost, long-term prospects for the semicon industry are testing. The alliance will pitch Japanese semicon companies favourably against American and European ones in cutting down design, R&D, and capital expenditure. Fujitsu and Toshiba have already announced that they are turning conservative to improve their bottom line.

 
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