Understanding SSTA

Ever thought why a design can work at much higher frequency than what the design team commits? And why doesn’t the design team quote this higher frequency as the achieved target?

Traditionally, Static Timing Analysis (STA) is used to analyze if a SoC can work at the desired frequency targets. The timing sign-off is done at the Worst Case (WCS) and Best Case (BCS) corners. Typically, these corners correspond to the 3-sigma corners. Invariably, to close timing at these corners lots of overdesigning might take place.

Statistical Static Timing Analysis (SSTA) tries to provide an answer to reduce this unnecessary overdesigning and hence makes an effort to make the design more realistic and help in increasing the frequency targets as well

SSTA
Basically, SSTA would calculate probability functions for the arrival time of each signal at each node. Based on the probability distribution function of the arrival time, it can be calculated if the design can meet the desired frequency target.

For example, if there is a 97 percent probability that the signal with the least slack has 5ns of arrival time, but only a 10 percent probability that it take 4ns. This essentially means that the yield for 200MHz frequency target is 97 percent whereas for 250MHz, it is 10 percent.

Why SSTA is better than traditional STA
Traditionally, static timing analysis (STA) has been the common way for closing timing of digital circuits over the last couple of decades.

However, as the geometry shrinks to 45nm and beyond, it is becoming increasingly difficult to close the timing. The increasing number of STA and process corners makes the situation more complex.

This complex situation arises because process variation is becoming extremely difficult at advanced technology nodes. There are two kinds of variations:
1. Die to Die
2. Intra Die

Both these variations can be further classified in to:
1. Systematic variation
2. Random variations

Some of these variations are currently accounted in traditional STA approach. SSTA tries to take all these kinds of variations in to account in terms of probability distribution.

Variations
With shrinking technology, the interconnect variation is becoming more dominant as compared to active gates. Their effect needs to be taken in to account while closing the timing for a SoC.

As interconnect became dominant, the critical variables in timing are not just transistors' critical dimensions, but also the dimensions and actual shapes of the wire segments and the number of nets that are in their vicinity.

Metal width, metal thickness, via resistance, and dielectric height, etc., are some of the metal layer properties that vary. Similar properties for the transistors are Transistor length, width, doping density and Gate oxide thickness.

1. Interconnect variation
The statistical approach models all possible combinations of variations in the interconnect space. For example, it is possible that the launch path is in METAL3 whereas the capture path is in METAL4.

Traditionally, STA would vary all metals together and thus can not model the scenario where the METAL3 is at a corner which results in max delay and the METAL4 is at the corner which results in min delay. Such a combination corresponds to the worst-case scenario for the setup paths and can only be captured by modeling the interconnect variations statistically.

2. Intra-die variation
Currently this is done using heuristic derate numbers and doing On-chip variation analysis with worst case and best case timing models.

3. Inter-die variation
These are the variations in the process parameters which can affect all the dies in a similar fashion. In STA, this is handled in terms of WCS timing models (slow transistors) and the BCS timing models (fast transistors)

Probability Density Function (PDF)
In SSTA all parameters (both random and systematic) are treated in terms of Probability distribution function (PDF).

That is, instead of using a single value, use probability density function. Example of the PDF is shown below in Figure1.


Figure 1: Probability density function of slack.
Click to enlarge

Example of timing path
A timing path is shown in Figure 2. The PDF for this timing path is shown in following Figure 3. This PDF is calculated after statistically analyzing the PDFs of gate delays and the arrival times.

Arrival times, slack, and slews, etc., are modeled using Taylor series.

a0 + ∑i=1,n (ai∂Gi) + an+1∂Ra

where,
– a0 is the mean value
– ∂Gi is the variation of “n” global sources
– ai depict the statistical variation for corresponding Gi
– ∂Ra is the variation of an independent random variable Ra
– an+1 depict the statistical variation for corresponding Ra

Mean (µ) = a0 + ∑i=1,n ai Mean(∂Gi)+ an+1Mean(∂Ra ) - (i)

Standard Deviation (σ) = [{ai Std(∂Gi)}2+ {an+1Std(∂Ra )}2]½ - (ii)

Using the above two equations the distribution functions can be constructed as shown below


Figure 2: Example of PDF.
Click to enlarge

The PDFs of gate delays (in RED) and arrival times (in GREEN) are also depicted in Figure 3.


Figure 3: Timing path.
Click to enlarge

PDF at OUT1
The area as shown represents the probability of timing violation. Essentially this area represents the loss of yield at current frequency targets. Such PDFs gives the answer to the questions mentioned in the 1st paragraph. Now the designer can claim the frequency numbers keeping the yield trade-off in account. Such advent can help to increase the margins of design companies because a closer frequency target can be claimed.


Figure 4: PDF for Timing Path
Click to enlarge

As shown in Figure 4, the PDF of the required and arrival times are combined to calculate the resulting distribution. Another point to note is that the clock delays are also expressed statistically before arriving.

SSTA difficulties
1. Probability functions are difficult to compute; more so because the variations on the die are not statistically independent of each other.
2. The calculation needs the timing models in S-lib format.
3. Because of huge statistical data, the calculation is memory intensive as compare to traditional STA
4. Run time also take a hit.

But all these difficulties can be accommodated keeping in mind the advantages that SSTA offers to the design community.

Summary
Still in nascent phase as compared to traditional STA, SSTA offers to get the closure of the design in a more realistic manner. It analyses the design due to complete process and interconnect parameter variations.