Modified DDS Functions as Baud-rate Generator

You can often use an available oscillator to generate a baud-rate clock for a UART. You must divide the oscillator frequency to attain the proper baud rate, but dividing can produce baud rate errors. Table 1 shows the percentage of error when you generate a baud rate using an 8-MHz crystal oscillator and a conventional binary divider. The system in this Design Idea obtains a clock 16 times faster than the baud rate.


Table 1

Errors in baud-rate setting increase when the oscillator frequency doesn’t match. In this case, you can add an oscillator operating at 18.432MHz, for example, to minimize the error rate. Alternatively, you can use DDS (direct digital synthesis) to reduce errors at higher baud rates using the same oscillator (Table 2).


Table 2

Reference 1 describes basic DDS operation. This design uses a simpler version of DDS with only a square-wave output (Figure 1). You can extract the square-wave output from the MSB of the phase accumulator. You can also add the divide-by-two stage to make the resulting signal with a 50 percent duty cycle. Calculate the baud-rate clock frequency using baud-rate clock= (reference clock×tuning word/2N)/2, where N is the number of bits for the phase accumulator.


Figure 1

Listing 1 is a Verilog implementation of the DDS baud-rate generator using a 20-bit phase accumulator and 16-bit tuning word.

Reference
1.“A Technical Tutorial on Direct Digital Synthesis,” Analog Devices, 1999.