ChipMOS Expands into 12in Wafer Gold Bumping

ChipMOS Technologies (Bermuda) Ltd has expanded its wafer gold bumping capabilities in Taiwan into 12-inch, high performance gold bumping production. In anticipation of the expected demand, the company plans to add a new, 12-inch gold bumping production line. ChipMOS currently expects facility and equipment setup of its 12-inch gold bumping line to be completed by the end of 2010 and the line will be ready for production at capacity of about 4,000 wafers per month, on top of the company's current 8-inch/6-inch gold bumping capacities. By the end of the third quarter of 2011, the 12-inch gold bumping capacity will ramp up to approximately 10,000 wafers per month.

"The decision to expand our high-performance, gold bumping capacity was driven by increasing demand for product applications, such as those used by smartphones," noted S.J. Cheng, Chairman and Chief Executive Officer, ChipMOS. "We believe this added capacity will better enable us to capture business opportunities in high resolution mobile display product segment. As an added bonus, we will also be able to utilize the 12-inch wafer gold bumping line for 8-inch wafer gold bumping production in order to address anticipated 8-inch capacity shortage. Importantly, since this line expansion was already factored into our capex plans as discussed in the most recent investor conference call, it will not result in any increase to our budget."

The company's investment in 12-inch gold bumping capability is designed to meet its customers' requirements to adopt 12-inch wafer manufacturing for next generation, one-chip-solution display driver products, which are primarily used in small display panels for mobile applications, including smartphones. Resolution has increased significantly in small display panels, requiring the density of integrated buffer frame memory in the one-chip-solution display driver to increase proportionally to support the multi-functionality of the IC. The result of which is a dramatically enlarged die size of the driver IC. The advantage of employing 12-inch wafer manufacturing technology is the ability to keep the display driver die size small by migrating into finer geometry, while decreasing manufacturing costs per chip via throughput enhancement at the same time. In addition, ChipMOS plans to migrate its existing 8-inch RDL (Re-Distribution Layer) capability into 12-inch together with this capacity expansion and provide more MCP (Multi-Chip Package) assembly flexibilities for mobile/niche DRAM or flash customers.

ChipMOS