Xilinx Extends FPGA Technology with Stacked Silicon Interconnect

Xilinx Inc. has launched the industry's first stacked silicon interconnect technology for delivering breakthrough capacity, bandwidth and power savings using multiple FPGA die in a single package for applications that require high-transistor and logic density, as well as tremendous levels of computational and bandwidth performance. By embracing 3D packaging technologies and through-silicon vias (TSV) for its 28nm 7 Series FPGAs, Xilinx's Targeted Design Platforms can address systems with resource requirements that are more than double the reach of the largest single-die FPGAs. This innovative platform approach enables Xilinx to overcome the boundaries of Moore's Law and offer electronics manufacturers unparalleled power, bandwidth and density optimization for the large-scale-integration of their systems.

"One of the ways the 28nm Xilinx 7 series FPGAs extend the range of applications programmable logic can address is by offering industry-leading capacity of up to 2 million logic cells. Our stacked silicon interconnect packaging approach makes this remarkable achievement possible," said Vincent Tong, Xilinx Senior Vice President. "Five years of Xilinx research and development coupled with industry leading technology from TSMC and our assembly suppliers has made possible our efforts to provide an innovative solution for enabling electronic systems developers to take the benefits of FPGAs further into their manufacturing flow."

With software support available in ISE Design Suite 13.1, which is currently available to beta customers, the 28nm Virtex-7 LX2000T device will be the world's first multi-die FPGA and provide more than 3.5X the logic capacity of the largest current-generation Xilinx 40nm FPGA with serial transceivers and 2.8X the logic capacity of the largest competing 28nm FPGA with serial transceivers. The device is made possible by industry-leading micro-bump assembly, patented FPGA architectural innovations from Xilinx, and advanced technology from TSMC that deliver lower levels of power consumption, system cost and circuit board complexity compared to using multiple FPGAs, each in their own package, for the same application.

Within the Xilinx stacked silicon interconnect structure, data flows between a set of adjacent FPGA die across more than 10,000 routing connections. Compared with having to use standard I/O connections to integrate two FPGAs together on a circuit board, stacked silicon interconnect technology provides over 100X the die-to-die connectivity bandwidth per watt, at one-fifth the latency, without consuming any high-speed serial or parallel I/O resources. By having die sit adjacent to each other and interfaced to the ball-grid-array, Xilinx can avoid the thermal flux and design tool flow issues that would be introduced had a purely vertical die-stacking approach been taken. Xilinx's choice of 28nm HPL (high-performance, low-power) process technology for the base FPGA device provides a comfortable power budget in the package for integrating FPGA die.

Xilinx stacked silicon interconnect technology serves the most demanding FPGA applications at the heart of next generation electronic systems. The technology's ultra high-bandwidth, low-latency and low-power interconnect allows customers to implement applications applying the same approaches used for large monolithic FPGA devices, using the software's built-in auto partitioning capabilities for push-button ease-of use, or hierarchical and team-based design techniques for the highest performance and productivity.

Xilinx Stacked Silicon Interconnect Technology

Xilinx

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