Synopsys to Expand Synthesis-based Test Technology

Synopsys Inc. plans to expand test technology embedded in Synopsys' RTL synthesis to address the need for higher defect coverage, lower test cost and faster yield analysis while simultaneously minimizing the impact on design goals and project schedules. Design teams currently using Synopsys' RTL synthesis and test solution are able to quickly implement compression to lower digital logic test costs, handle pin-limited test methodologies and execute on-chip testing of high-speed blocks like USB and PCI Express cores.

Commencing today and continuing over the next 12 months, Synopsys is rolling out expanded synthesis-based test technology to provide defect coverage of embedded memories, lower test cost significantly with higher compression for pin-limited test and extremely large designs, and enable designers to rapidly analyze defective silicon devices. As with Synopsys' widely-deployed DFTMAX compression, the new test technology will enable designers to achieve optimal quality-of-results and eliminate time-consuming iterations between design and test.

Testing complex chips requires embedding dedicated test logic throughout the entire design. Implementing this test logic outside the synthesis flow adversely impacts design characteristics such as performance and power consumption, leading to iterations between synthesis and test that lengthen project schedules. In contrast, Synopsys' solution implements test within RTL synthesis to minimize the impact on design power, timing and area, accelerating convergence on both design and test goals. Synopsys is expanding this synthesis-based test technology to further increase designer productivity, improve quality and lower cost across all areas of manufacturing test and yield analysis, including the following:

- Memory Test and Repair
In widespread use today, the DesignWare STAR Memory System delivers high-coverage test and repair of embedded memories. Synopsys plans tighter integration with synthesis-based test to ensure fast turnaround time and maximum scalability.

- Higher Compression
To accommodate the need for even lower test cost for pin-limited methodologies as well as extremely large designs, Synopsys will provide higher compression utilizing synthesis-based technology to maximize designer productivity.

- Faster Yield Analysis
New integration between TetraMAX ATPG and Yield Explorer yield analysis will enable designers to rapidly debug defective parts from a relatively small number of wafers.

Synopsys

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