Development of AXI-based CAN IP

Xilinx Inc. is one of the world’s leading suppliers of programmable logic devices (PLDs) to the automotive market. The company offers a full line of industrial-grade and automotive-qualified PLDs, reference designs and development boards, along with a strong ecosystem. One of Xilinx’s keys to success in this market is its comprehensive library of IP (intellectual property) cores that allow customers to take advantage of the scalable and flexible nature of the PLD architecture and bring new, innovative features the automotive industry.

The Xilinx India team is an integral part of this IP development. Very recently, the team developed the Xilinx CAN IP core, which is suited to applications in-vehicle networking, automotive test equipment, instrument clusters, sensor controls, and industrial networks. The team made the core highly flexible, giving it many user-configurable options. In addition, customers can use the core in stand-alone mode or connect it to Xilinx MicroBlaze or PowerPC processors.

Figure 1 shows a high level block diagram of the CAN controller. Some of the key features include configurable transmit and receive buffers, acceptance filtering, transmit high priority buffer and maskable error and status interrupts.


Figure 1: CAN block diagram.

The Xilinx India team was responsible for identifying the core’s features, architecting and designing the core, and, ultimately, verifying its functionality—which is the biggest challenge for the team. To deal with this issue, the India team employed a relatively new verification methodology called OVM (Open Verification Methodology). Using OVM, the team architected and developed the verification environment and exhaustively defined functional coverage for controller and constraint-based randomization techniques in the test environment. Using this methodology, the team focused on collecting metrics and details on functional coverage, code coverage, simulation cycles, lines of code and bugs. They used this data to monitor the health of the core and to track verification progress. Powerful automation scripts helped the team test the core thoroughly and collect the metrics effectively.

The group also thoroughly validated the core using industry-standard network analyzers to ensure it meet the CAN standard’s specification.

AXI System
Apart from designing the original Xilinx CAN IP core, the team also integrated the industry standard AXI-4 interface to the CAN controller – giving the core flexible connectivity options using the AXI interconnect. AXI is part of ARM’s AMBA (Advanced Microcontroller Bus Architecture) family of buses and is an interface definition that is used for connecting individual pieces of IP. Xilinx has built a piece of parameterizable IP that will connect AXI (MM and LITE) masters with AXI (MM and LITE) slaves. This IP is called an “interconnect.” AXI masters could be MicroBlaze or other soft IP capable of AXI bus mastering (i.e. DMA Controllers), while AXI slaves are most soft AXI peripherals. The interconnect that Xilinx built is capable of connecting with AXI-3, AXI-4 MM and AXI-4 LITE.

AXI-4 is a point to point, master/slave interface. The AXI-4 specification includes three different AXI interface types: memory-mapped (MM), streaming (STR) and Lite (LITE). A typical system consists of a number of master and slave devices connected together through some form of interconnect.

The AXI protocol provides a single interface definition for describing interfaces:
- between a master and the interconnect
- between a slave and the interconnect
- between a master and a slave

Each AXI channel transfers information in only one direction, and there is no requirement for a fixed relationship between the various channels. This is important because it enables the insertion of a register slice in any channel at the cost of an additional cycle of latency. This makes possible a trade-off between cycles of latency and maximum frequency of operation. It is also possible to use register slices at almost any point within a given interconnect. It can be advantageous to use a direct, fast connection between a processor and high-performance memory, but to use simple register slices to isolate a longer path to less performance-critical peripherals.

In Figure 2, the MicroBlaze processor is the AXI system master, and the DDR3 controller sits on the AXI Full interconnect. The application runs out of the DDR3 memory. The CAN controller and the IIC controllers both sit on the AXI Lite interconnect. MDM (Micro-Blaze Debugger) is useful to debug the design using the JTAG interface.


Figure 2: Typical AXI system with CAN controller.

With innovative cores such as the new AXI CAN core, Xilinx’s automotive customers can bring innovative electronic features to the market faster than before.