Synopsys Enables Full Chip Transistor Level Timing Analysis on Cavium Processors

Cavium Networks Inc. has utilized Synopsys Inc.'s NanoTime transistor-level static timing analysis (STA) solution to achieve full-chip STA signoff for its next-generation internet application processor, OCTEON II. The multi-core, high speed OCTEON II processor is optimized for high performance network packet processing and low power consumption. Targeted for scalable networking equipment designed to fuel the voice, video and data convergence driven by cloud computing, the OCTEON II required extremely accurate timing verification in order to meet the demanding frequency target. Synopsys' NanoTime transistor-level static timing analysis (STA) solution was used extensively to deliver timing verification coverage with a degree of accuracy that correlated within plus-minus five percent of HSPICE circuit simulator.

NanoTime is the next-generation transistor-level static timing analysis solution that addresses the challenge of signal integrity (SI) analysis associated with custom designs. NanoTime offers concurrent timing and SI analysis with accuracy within plus-minus five percent of HSPICE, and delivers the performance required to analyze complex transistor circuits overnight. The advanced features in NanoTime enable designers to accurately and quickly identify timing issues early in the design phase to avoid expensive silicon re-spins. Its seamless integration with Synopsys' PrimeTime product enables full-chip analysis of designs that includes both gate level and transistor-level blocks. This combination of PrimeTime and NanoTime delivers the industry's most comprehensive solution for full chip static timing signoff for today's complex systems-on-chips (SoCs).

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