Open-Silicon Tapes Out 2.4GHz ASICs Using Cadence Silicon Realization Technology

Open-Silicon Inc. has successfully taped out a breakthrough high-performance processor at over 2.4GHz under typical conditions utilizing Cadence Design Systems (India) Pvt Ltd's Cadence Silicon Realization product line. Cadence Design Systems (India) is a subsidiary of Cadence Design Systems Inc.

Open-Silicon completed the entire design using Cadence’s integrated end-to-end Encounter digital design, implementation, and manufacturability signoff technology.

“Cadence offers a complete suite of tools for designing ASICs and strong customer support. We have fine tuned the tools and found good results from synthesis through to tapeout. Cadence’s Silicon Realization technology has also been a key contributor to our ongoing efforts to increase our predictability and reliability, both of which are critical to the Open-Silicon custom silicon solution,” said Taher Madraswala, Vice President of Engineering at Open-Silicon.

Open-Silicon’s chips go into products where performance, power and time-to-market are paramount. Cadence’s Silicon Realization product line optimizes logical, physical, electrical, and manufacturing effects concurrently, eliminating iteration without sacrificing design quality by addressing timing sensitivity, yield variation, and leakage power from the start, thereby achieving the objectives of performance, power, and cost.

“We see Cadence as a key collaborator for Open-Silicon as we move towards 28nm design and as the industry moves towards a design-lite model,” said Dr. Naveed Sherwani, President and CEO of Open-Silicon. “We are confident that working with Cadence will help us achieve our customers’ specific goals.”

Cadence recently announced a new holistic approach to Silicon Realization that moves chip development beyond its traditional patchwork of point tools to a streamlined end-to-end path of integrated technology, tools, and methodology. The new approach is focused on offering products and technologies that deliver on the three essential requirements for a deterministic path to silicon: unified design intent, abstraction and convergence. A key element of the Cadence EDA360 strategy, this approach is aimed at boosting productivity, predictability and profitability while reducing risk.

Cadence

Open-Silicon

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