Ultra-thin Alternative to Silicon Claimed

Researchers with the US Department of Energy's Lawrence Berkeley National Laboratory (Berkeley Lab) and the University of California (UC) Berkeley are continuing work toward an alternative to silicon and have claimed successfully integration of ultra-thin layers of the semiconductor indium arsenide (InAs) onto a silicon substrate to create a nanoscale transistor with what they describe as "excellent" electronic properties.

InAs, a member of the III-V family of semiconductors, is considered by some to have advantages as an alternative to silicon, including superior electron mobility and velocity. The researchers claim to have a simple route for the heterogeneous integration of InAs layers down to a thickness of 10nm on silicon substrates.

"The devices we subsequently fabricated were shown to operate near the projected performance limits of III-V devices with minimal leakage current," Ali Javey, a faculty scientist in Berkeley Lab's Materials Sciences Division and a professor of electrical engineering and computer science at UC Berkeley who led the research, said in a statement. "Our devices also exhibited superior performance in terms of current density and transconductance as compared to silicon transistors of similar dimensions."

The research group focused on compound III-V semiconductors and noted that a main challenge for use has been to find a way of plugging these compound semiconductors into the processing technology used to produce today's silicon-based devices. The researchers explained that, given the large lattice mismatch between silicon and III-V compound semiconductors, direct hetero-epitaxial growth of III-V on silicon substrates is complex and often results in a high volume of defects.

"We've demonstrated what we are calling an ‘XOI,' or compound semiconductor-on-insulator technology platform, that is parallel to today's ‘SOI,' or silicon-on-insulator platform," Javey said. "Using an epitaxial transfer method, we transferred ultrathin layers of single-crystal indium- arsenide on silicon/silica substrates, then fabricated devices using conventional processing techniques in order to characterize the XOI material and device properties."

As described by Berkeley Lab, the researchers grew single-crystal InAs thin films 10- to 100-nm thick on a preliminary source substrate then lithographically patterned the films into ordered arrays of nanoribbons. After being removed from the source substrate through a selective wet-etching of an underlying sacrificial layer, the nanoribbon arrays were transferred to the silicon/silica substrate via a stamping process, Berkeley Lab said.

Javey attributed the electronic performance of the XOI transistors to the small dimensions of the active "X" layer and the critical role played by quantum confinement, which served to tune the material's band structure and transport properties. Although he and his group only used InAs as their compound semiconductor, they said the technology should readily accommodate other compound III/V semiconductors, as well.

"Future research on the scalability of our process for 8-inch and 12-inch wafer processing is needed," Javey admitted. "Moving forward we believe that the XOI substrates can be obtained through a wafer bonding process, but our technique should make it possible to fabricate both p- and n-type transistors on the same chip for complementary electronics based on optimal III-V semiconductors.

"Furthermore, this concept can be used to directly integrate high-performance photodiodes, lasers, and light-emitting diodes on conventional silicon substrates. Uniquely, this technique could enable us to study the basic material properties of inorganic semiconductors when the thickness is scaled down to only a few atomic layers," he concluded.

The research was funded in part by a grant from the Berkeley Lab, and by the MARCO/MSD Focus Center at MIT, Intel Corp, and the Berkeley Sensor and Actuator Center.