Cadence Accelerates Billion-plus Gate Design

Cadence Design Systems Inc. has advanced the design of giga-gate/gigahertz system-on-chips (SoCs) with a proven digital end-to-end flow at 28nm that yields both performance and time-to-market advantages. Driven by the Cadence Silicon Realization approach, the new Encounter-based flow provides a faster, more deterministic path to achieve giga-gate/gigahertz silicon through technology integration and significant core architecture and algorithm improvements in a unified design, implementation and verification flow.

Working seamlessly with Cadence’s analog/mixed-signal and silicon/package co-design domains, the new digital 28nm flow enables designers to consider the entire chip flow holistically to drive breakthroughs in high-performance, low-power, mixed-signal, and even 3D-IC designs- critical success factors for mobility-based and multimedia SoCs.

The new flow supports Cadence’s approach to Silicon Realization through its focus on unique and pervasive design intent, abstraction, and convergence from RTL to GDSII, then through to packaging. Silicon Realization is a key element of the EDA360 vision.

“Twenty-eight-nanometer process technology is both a great opportunity and challenge for designers, with its power, performance and area advantages coupled with challenges such as process variation and new manufacturing effects,” said Albert Li, Director of Design and Development at Global Unichip Corp. “We used the Cadence digital end-to-end flow for our first 28nm design because Cadence’s commitment to giga-gates/gigahertz design capabilities and advanced technology nodes is what we need to serve our customers. Using the Cadence digital end-to-end flow, we are able to not only handle the complex routing, variability and manufacturing requirements of 28nm designs, but also tackle 100+ million gate designs within a reasonable design cycle time. The end result is more productivity and better schedule predictability on our deliverables to our customers.”

Eliminating the need for trade-offs between complexity and advanced process nodes, the new flow optimizes complex design at 28nm, providing a path for advanced SoC development to realize the cost benefits of smaller geometries. Key to the flow’s performance is a unified digital design, implementation, and verification based on intent, abstraction, and convergence.

The flow features complete, silicon-proven 28nm design rule intent (electrical, physical, DFM) with early, upfront trade-off analysis, and a 2x improvement in routing runtime through intelligent via and pin-density optimizations. It also has early clock topology intent capture and planning that uses physical information to intelligently optimize clock gating and balance clock trees throughout the design during synthesis.

The solution also offers breakthrough data abstraction technologies that enable entire blocks of logic to be modeled simply and accurately, and optimized across logical and physical domains, for giga-gate scalability and design productivity. Its support for hierarchical low-power and OpenAccess-based mixed-signal quick/detailed abstractions enable rapid integration of IP and advanced SoCs.

“The complexity of 28nm design coupled with the need to support complex giga-gate/gigahertz requirements demands an integrated end-to-end flow,” said David Desharnais, Senior Director, Silicon Realization product marketing. “Our unique Silicon Realization approach allows our customers to push their SoC designs to new levels in order to deliver the highest performance silicon for multimedia, communications and computing applications. The announcement of our comprehensive 28nm digital Silicon Realization flow continues our push toward realizing the EDA360 vision.”

The Encounter-based Silicon Realization digital end-to-end flow includes technologies such as Encounter RTL Compiler, Encounter Digital Implementation System, Encounter Conformal technologies, Encounter Test, Encounter Timing System, Cadence QRC Extraction, Encounter Power System and Encounter DFM technologies.

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