Synopsys DDR Memory Controller Tool Enables Faster Access to Off-chip DRAM

Synopsys Inc. has released its enhanced DesignWare Universal DDR Memory Controller, which delivers up to 30 percent lower latency and offers up to 15 percent higher throughput than the previous generation controller.

The DDR Memory Controller offers new features such as high-priority bypass and configurable 'look-ahead.' The high-priority bypass option allows designers to improve latency by bypassing the scheduling algorithm, allowing immediate access to the DRAM. The configurable 'look-ahead' feature provides intelligent scheduling to maximize throughput by prioritizing out-of-order transactions to the DRAM, allowing designers to make trade-offs between area and performance.

The Memory Controller also offers a DFI 2.1-compliant interface to the DDR PHY, delivers memory system performance of up to 2.133Gbps and supports the DDR3, DDR2, LPDDR and LPDDR2 SDRAM standards.


The DesignWare Universal DDR Memory Controller is part of Synopsys' comprehensive DesignWare DDR IP offering that consists of digital controllers and PHY IP supporting DDR, DDR2, DDR3, LPDDR and LPDDR2. The DesignWare DDR IP supports leading 130, 90, 65, 55, 45/40 and 32/28nm technologies.

Synopsys