Make a Quick-turnaround PCB for RF Parts

Using low-cost PCBs (printed-circuit boards), you can easily design a board in a few hours with nearly any CAD package, even the free ones. You can have your prototype board on your desk in just two days. The design rules in many software packages are good, and most suppliers can fabricate a PCB with line width and spacing down to 0.006in.

That precision is fine for low-frequency circuits, but RF circuits usually need 50Ω traces for proper circuit operation. Parts get smaller, but the laws of physics don’t change. Thus, a microstrip trace on a 0.062in-thick standard prototype board that was calculated to be 0.11in wide 30 years ago is still 0.11 in. wide today. Many surface-mount parts are far smaller than their predecessors, however, so it would seem that low-cost, two-layer prototype boards for RF prototyping are unsuitable for today’s small SMT (surface-mount-technology) parts.

You can use a CPWG (coplanar-waveguide-over-ground) structure to build 50Ω RF traces on PCBs. A CPWG structure lets you make the required trace width smaller than that of a microstrip structure.

Bringing a grounded copper ground plane on the top of the board closer to a microstrip trace adds capacitance to the microstrip structure. To compensate and to keep the entire structure at 50Ω, you must make the center trace more inductive by reducing its width—to a point.

How can you design the CPWG structure for a low cost and a fast PCB process? You can find many online CPWG calculators, but they often fail when the ground-plane gap gets less than approximately 30 to 50% of the trace width because the height of the copper traces on the board becomes a significant factor. It adds more capacitance than the calculators assume. Hence, the lines these calculators design have too much capacitance, which reduces their impedance to less than 50Ω. The equations date back many years to IC design.

The equations in many calculators fall apart because today PCBs differ physically from ICs. The best way to properly design a CPWG on a PCB with a narrow gap-to-center-trace ratio is to use a full 3D electromagnetic simulator. This Design Idea provides the values for a few common structures.

In keeping with the minimum trace-to-trace spacing of 6 mils, I simulated, built, and tested a CPWG structure. For a common 0.062in-thick FR-4 PCB material, a trace width of 0.032in with a gap of 0.006in is as close to 50Ω as you can get. It provides better than 40-dB return loss on the trace at 6GHz.

This approach is better than using a 0.11in-wide trace and is compatible with SMT-sized parts. A 0603-sized SMT part and a common SMA (surface-mount-assembly) edge-launch connector fit the line perfectly. Figure 1 compares several common RF-type parts with the fabricated PCB. For parts with larger pad dimensions than the 0.032in trace width, just increase the spacing to the top ground plane to compensate. For instance, increase the spacing to the top plane of a 0805 SMT pad to approximately 0.008in and increase the top-plane spacing for a 1206 SMT-component pad to 0.012in to keep the pad from being too capacitive.

In keeping with common design rules, I pulled back the copper planes on the tested PCBs 0.01in from the routed board edge. This pull-back and the edge-launch connector both add a slight amount of inductance to the transition, however. The big center pin of the edge-launch connector on top of the trace adds extra capacitance, providing built-in capacitive compensation. Cutting the pin to about half its original length yields about equal capacitance to balance the transition inductance.

The CPWG structure needs a solid ground plane under the trace; leaving cutouts in the bottom ground plane under the topside trace adds a significant inductance to the structure, which degrades high-frequency performance. You also need to “stitch” the top ground plane to the bottom ground plane with vias. Place the stitching vias less than one-eighth of a wavelength of the highest frequency that your circuit will use. Note that 0.1in spacing works well at frequencies greater than 10GHz.

Spacing of the stitching vias to the center trace follows the same spacing rules. You can easily get enough vias in and around the trace to make it work.

If you don’t have enough vias, you will see a slight but rapid 0.5dB to 1dB drop in the S21 transmission characteristics instead of a linear loss slope with frequency. You can instantly see this effect by using a VNA (vector network analyzer). Measuring the test board shows approximately 0.25dB/in of loss at 3GHz and 1dB/in of loss at 10GHz, including two edge-launch connectors.

To interface to an SMT part or an IC with narrower pads than 0.032in, narrow down the center conductor as needed as close to the part as possible. If the discontinuity is physically small, it will have little effect until very high frequencies.